Renesas H8S/2158, User Manual

Page: 164 / 929

Section 6 Bus Controller
Rev. 3.00 Jan 25, 2006 page 110 of 872
REJ09B0286-0300
6.3.3 Wait State Control Register (WSCR)
WSCR is used to specify the data bus width for external address space access, the number of
access states, the wait mode, and the number of wait states for access to external address spaces
(basic expansion area and 256-kbyte expansion area). The bus width and the number of access
states for internal memory and internal I/O registers are fixed regardless of the WSCR settings.
Bit Bit Name Initial Value R/W Description
7 ABW256 1 R/W 256-kbyte Expansion Area Bus Width Control
Selects the bus width for access to the 256-kbyte
expansion area when the CS256E bit in SYSCR is set
to 1.
0: 16-bit bus
1: 8-bit bus
6 AST256 1 R/W 256-kbyte Expansion Area Access State Control
Selects the number of states for access to the 256-
kbyte expansion area when the CS256E bit in SYSCR
is set to 1. This bit also enables or disables wait-state
insertion.
0: 2-state access space. Wait state insertion disabled in
256-kbyte expansion area access
1: 3-state access space. Wait state insertion enabled in
256-kbyte expansion area access
5 ABW 1 R/W Bus Width Control
Selects the bus width for access to the basic expansion
area.
0: 16-bit bus
1: 8-bit bus
When the CS256E bit in SYSCR and the CPCSE bit in
BCR2 are set to 1, this bit setting is ignored in 256-
kbyte expansion area access and CP/CF expansion
area access.