Renesas H8S/2158, User Manual

Page: 815 / 929

Section 26 Clock Pulse Generator
Rev. 3.00 Jan 25, 2006 page 761 of 872
REJ09B0286-0300
Section 26 Clock Pulse Generator
This LSI incorporates a clock pulse generator which generates the system clock (
φ
), internal clock,
bus master clock, and subclock (
φ
SUB). The clock pulse generator consists of an oscillator, duty
correction circuit, system clock select circuit, medium-speed clock divider, bus master clock select
circuit, subclock input circuit, and waveform forming circuit. Figure 26.1 shows a block diagram
of the clock pulse generator.
This LSI also incorporates a PLL (Phase Locked Loop) circuit that generates a 48-MHz clock
(
φ
48) and a 24-MHz clock (
φ
24) as the USB operating clock. The 24-MHz clock can be used as
the system clock (
φ
) by inputting it to the duty correction circuit instead of the oscillator output to
which the EXTAL and XTAL pins are input. The PLL circuit consists of a USB external clock
input circuit, PLL input clock select circuit, division/multiplication circuit, and USB operating
clock select circuit.
WDT_1
count clock
System clock
To
φ
pin
Internal clock
To peripheral
modules
Bus master clock
To CPU and DTC
EXTAL
PLL circuit
XTAL
EXCL
φ
USEXCL
φ
/2
to
φ
/32
φ
SUB
φ
24
φ
24
φ
48
φ
48
φ
Oscillator
Duty
correction
circuit
USB external
clock input
circuit
PLL input
clock select
circuit
USB operating clock
To USB
USB operating
clock select
circuit
Division/
Multiplication
circuit
Subclock
input circuit
Waveform
forming
circuit
System clock
select circuit
Medium-
speed clock
divider
Bus master
clock select
circuit
Figure 26.1 Block Diagram of Clock Pulse Generator
The bus master clock is selected as either high-speed mode or medium-speed mode by software
according to the settings of the SCK2 to SCK0 bits in the standby control register. Use of the
medium-speed clock (
φ
/2 to
φ
/32) may be limited during CPU operation and when accessing the
internal memory of the CPU. The operation speed of the DTC and RFU and the external space
access cycle are thus stabilized regardless of the setting of medium-speed mode. For details on the
standby control register, see section 27.1.1, Standby Control Register (SBYCR).
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