Renesas H8S/2158, User Manual

Page: 827 / 929

Section 27 Power-Down Modes
Rev. 3.00 Jan 25, 2006 page 773 of 872
REJ09B0286-0300
Bit Bit Name Initial Value R/W Description
6
5
4 STS2
STS1
STS0 0
0
0 R/W
R/W
R/W Standby Timer Select 2 to 0
Select the wait time for clock stabilization from clock
oscillation start when canceling software standby mode,
watch mode, or subactive mode. Select a wait time of 8 ms
(oscillation stabilization time) or more, depending on the
operating frequency. Table 27.1 shows the relationship
between the STS2 to STS0 values and wait time.
With an external clock, there are no specific wait
requirements. Normally the minimum value is
recommended.
3 DTSPEED 0 R/W DTC/RFU Speed
Specifies the operating clock for the bus masters (DTC and
RFU) other than the CPU in medium-speed mode.
0: All bus masters operate based on the medium-speed
clock.
1: The DTC/RFU operates based on the system clock.
The operating clock is changed when a DTC/RFU transfer
is requested even if the CPU operates based on the
medium-speed clock. Note however that medium-speed
mode for the RFU is not supported in this LSI. This bit must
be set to 1 when the RFU is used in medium-speed mode.
If the RFU is activated while this bit is cleared to 0, the
program may go wild.
2
1
0 SCK2
SCK1
SCK0 0
0
1 R/W
R/W
R/W System Clock Select 2 to 0
Select a clock for the bus master in high-speed mode or
medium-speed mode.
When making a transition to subactive mode or watch
mode, the SCK2 to SCK0 bits must be cleared to B’000.
000: High-speed mode
001: Medium-speed clock:
φ
/2 (Initial value)
010: Medium-speed clock:
φ
/4
011: Medium-speed clock:
φ
/8
100: Medium-speed clock:
φ
/16
101: Medium-speed clock:
φ
/32
11X: —
Legend:
X: Don't care