Renesas H8S/2158, User Manual

Page: 334 / 929

Section 11 14-Bit PWM Timer (PWMX)
Rev. 3.00 Jan 25, 2006 page 280 of 872
REJ09B0286-0300
11.4 Bus Master Interface
DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the
on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these
registers, it therefore uses an 8-bit temporary register (TEMP).
These registers are written to and read from as follows.
•
Write
When the upper byte is written to, the upper-byte write data is stored in TEMP. Next, when the
lower byte is written to, the lower-byte write data and TEMP value are combined, and the
combined 16-bit value is written in the register.
•
Read
When the upper byte is read from, the upper-byte value is transferred to the CPU and the
lower-byte value is transferred to TEMP. Next, when the lower byte is read from, the lower-
byte value in TEMP is transferred to the CPU.
These registers should always be accessed 16 bits at a time with a MOV instruction, and the upper
byte should always be accessed before the lower byte. Correct data will not be transferred if only
the upper byte or only the lower byte is accessed. Also note that a bit manipulation instruction
cannot be used to access these registers.
Example 1: Write to DACNT
MOV.W R0, @DACNT ; Write R0 contents to DACNT
Example 2: Read DADRA
MOV.W @DADRA, R0 ; Copy contents of DADRA to R0
Table 11.2 Read and Write Access Methods for 16-Bit Registers
Read Write
Register Name Word Byte Word Byte
DADRA and DADRB Yes Yes Yes
×
DACNT Yes
×
Yes
×
Legend: Yes: Permitted type of access. Word access includes successive byte accesses to the
upper byte (first) and lower byte (second).
×
: This type of access may give incorrect results.