Renesas H8S/2158, User Manual

Page: 565 / 929

Section 17 I
2
C Bus Interface (IIC)
Rev. 3.00 Jan 25, 2006 page 511 of 872
REJ09B0286-0300
Table 17.5 Restrictions on Accessing IIC Registers
Register Bit Bit Name R/W Description
ICDR 7 to 0 — R/W Writing is disabled. Reading/writing to this
register does not initiate any data transfer.
Writing has no affect on the bits.
7 to 1 SVA6 to SVA0 R/W Write the slave address. SAR
0 FS R/W Select the I
2
C bus format.
7 to 1 SVAX6 to SVAX0 R/W Write the second slave address as required. SARX
0 FSX R/W Select the I
2
C bus format.
7 MLS R/W Select MSB-first.
6 WAIT R/W The value written to this bit is ignored because
the function of this bit is replaced by ICCMD.
The function of this bit can be monitored by the
WAITX bit in ICSRA.
5 to 3 CKS2 to CKS0 R/W Select the transfer rate.
ICMR
2 to 0 BC2 to BC0 R/W Set to B'000 (9 bits).
7 ICE R/W —
6 IEIC R/W Even when set to 1, the conventional interrupt
is ignored.
5
4
3 MST
TRS
ACKE R/W
R/W
R/W The values written to these bits are ignored
because the functions of these bits are
replaced by ICCMD. The functions of these bits
can be monitored by the MSTX, TRSX, and
ACKXE bits in ICSRA.
2 BBSY R/W Writing B'10 or B'00 is ignored.
1 IRIC R/W —
ICCR
0 SCP W Writing B'10 or B'00 is ignored.
7
6
5
4
3
2
1 ESTP
STOP
IRTR
AASX
AL
AAS
ADZ R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W) — ICSR
0 ACKB R/W The value written to this bit is ignored because
the function of this bit when written to is
replaced by the ACKXB bit in ICCRX.