Renesas H8S/2158, User Manual

Page: 107 / 929

Section 2 CPU
Rev. 3.00 Jan 25, 2006 page 53 of 872
REJ09B0286-0300
BCLR instruction executed
BCLR #0, @P4DDR
The BCLR instruction is executed for DDR in port 4
After executing BCLR
P47 P46 P45 P44 P43 P42 P41 P40
Input/output Output Output Output Output Output Output Output Input
Pin state Low
level High
level Low
level Low
level Low
level Low
level Low
level High
level
DDR 1 1 1 1 1 1 1 0
DR 1 0 0 0 0 0 0 0
[Description on Operation]
1. When the BCLR instruction is executed, first the CPU reads P4DDR.
Since P4DDR is a write-only register, so the CPU reads H'FF. In this example P4DDR has a
value of H'3F, but the value read by the CPU is H'FF.
2. The CPU clears bit 0 of the read data to 0, changing data to H'FE.
3. The CPU writes H'FE to DDR, completing execution of BCLR.
As a result of the BCLR instruction, bit 0 in DDR is set to 0, and P40 becomes an input pin.
However, bits 7 and 6 of DDR are modified to 1, therefore P47 and P46 become output pins.