Section 18 Universal Serial Bus Interface (USB)
Rev. 3.00 Jan 25, 2006 page 615 of 872
REJ09B0286-0300
USB Host
USB Function Core
Slave CPU
Core Interface
Notes: 1. When an EP2TF interrupt is specified as a USBIB or USBIC interrupt according to the INTSELR0 setting, the corresponding interrupt occurs.
In this case, if a USBIB or USBIC interrupt occurs, interrupt source determination process is not required. (Note that TFFR0 must be
accessed to clear the flags.)
2. When an EP2TS interrupt is specified as a USBIB or USBIC interrupt according to the INTSELR0 setting, the corresponding interrupt occurs.
In this case, if a USBIB or USBIC interrupt occurs, interrupt source determination process is not required. (Note that TSFR0 must be
accessed to clear the flags.)
Receive a NAK
handshake packet
Send NAK to the host CPU
Send NAK to the slave CPU
Request an USBID
interrupt (EP2TF)
*
1
Initiate the USBID interrupt
processing
Read USBIFR0 and check
if a TF interrupt occurs
or not
Read TFFR0 and check
if an EP2TF interrupt occurs
or not
Read FVSR2 and write data
to EPDR2 for the number
of bytes which can be
written to the EP2 FIFO
Write data to the EP2 FIFO
Complete the USBID
interrupt processing
Send an IN token packet
Receive an IN data
packet (8 bytes)
Re-transmission
Modify FVSR2
Modify FVSR2 and enable
data transmission
Send an IN token packet
Disable data read
because the EP2 FIFO is
empty
Set the EP2TE bit of
PTTER0 to 1
Read data from the EP2
FIFO
Receive an ACK
handshake packet
Send ACK to the slave CPU
Request an USBID
interrupt (EP2TS)
*
2
Initiate the USBID
interrupt processing
The following procedure is
the same as that when
the initial FIFO is full.
Receive an IN token packet
Clear the EP2TF bit of
TFFR0 to 0
Receive an IN data
packet (8 bytes)
Receive ACK
Receive an IN token packet
Figure 18.11 Operation on Receiving an IN Token (EP2-IN: Initial FIFO Is Empty)
Summary of Contents for H8S/2158
Page 10: ...Rev 3 00 Jan 25 2006 page viii of lii...
Page 36: ...Rev 3 00 Jan 25 2006 page xxxiv of lii B Product Lineup 863 C Package Dimensions 864 Index 865...
Page 47: ...Rev 3 00 Jan 25 2006 page xlv of lii Appendix Figure C 1 Package Dimensions TBP 112A 864...
Page 54: ...Rev 3 00 Jan 25 2006 page lii of lii...
Page 70: ...Section 1 Overview Rev 3 00 Jan 25 2006 page 16 of 872 REJ09B0286 0300...
Page 118: ...Section 3 MCU Operating Modes Rev 3 00 Jan 25 2006 page 64 of 872 REJ09B0286 0300...
Page 126: ...Section 4 Exception Handling Rev 3 00 Jan 25 2006 page 72 of 872 REJ09B0286 0300...
Page 198: ...Section 6 Bus Controller Rev 3 00 Jan 25 2006 page 144 of 872 REJ09B0286 0300...
Page 326: ...Section 10 8 Bit PWM Timer PWM Rev 3 00 Jan 25 2006 page 272 of 872 REJ09B0286 0300...
Page 440: ...Section 15 Watchdog Timer WDT Rev 3 00 Jan 25 2006 page 386 of 872 REJ09B0286 0300...
Page 606: ...Section 17 I 2 C Bus Interface IIC Rev 3 00 Jan 25 2006 page 552 of 872 REJ09B0286 0300...
Page 742: ...Section 19 Multimedia Card Interface MCIF Rev 3 00 Jan 25 2006 page 688 of 872 REJ09B0286 0300...
Page 750: ...Section 21 D A Converter Rev 3 00 Jan 25 2006 page 696 of 872 REJ09B0286 0300...
Page 768: ...Section 22 A D Converter Rev 3 00 Jan 25 2006 page 714 of 872 REJ09B0286 0300...
Page 770: ...Section 23 RAM Rev 3 00 Jan 25 2006 page 716 of 872 REJ09B0286 0300...
Page 824: ...Section 26 Clock Pulse Generator Rev 3 00 Jan 25 2006 page 770 of 872 REJ09B0286 0300...
Page 844: ...Section 27 Power Down Modes Rev 3 00 Jan 25 2006 page 790 of 872 REJ09B0286 0300...
Page 878: ...Section 28 List of Registers Rev 3 00 Jan 25 2006 page 824 of 872 REJ09B0286 0300...
Page 926: ...Index Rev 3 00 Jan 25 2006 page 872 of 872 REJ09B0286 0300...