Section 18 Universal Serial Bus Interface (USB)
Rev. 3.00 Jan 25, 2006 page 581 of 872
REJ09B0286-0300
18.3.11 USB Control /Status Register 0 (USBCSR0)
USBCSR0 controls the operation of the USB function core.
USBCSR0 is initialized to H'00 by a system reset or function software reset (see section 18.3.16,
USB Control Registers 0 and 1 (USBCR0, USBCR1)).
Bit
Bit Name Initial Value R/W
Description
7 to 4 —
All 0
R
Reserved
These bits are always read as 0 and cannot be modified.
3
EP0STOP 0
R/W
Endpoint 0 Stop
Used to protect the contents of endpoint 0 FIFO in the
USB function core. Setting this bit to 1 protects the data
that is sent to the EP0 OUT-FIFO by a SETUP
transaction.
0: Indicates that the EP0 OUT-FIFO and specific FIFO is
in an operating state.
[Clearing conditions]
•
System
reset
•
Function
software
reset
1: Indicates that the EP0 OUT-FIFO is in a read stop
state.
[Setting conditions]
•
FVSR0O contents are not changed by reading
EPDR0O.
Indicates that the EP0 specific FIFO is in a write or
transfer stop state.
•
FIFO contents are not changed by writing to EPDR0I.
•
FVSR0I contents are not changed by setting EP0ITE.
Summary of Contents for H8S/2158
Page 10: ...Rev 3 00 Jan 25 2006 page viii of lii...
Page 36: ...Rev 3 00 Jan 25 2006 page xxxiv of lii B Product Lineup 863 C Package Dimensions 864 Index 865...
Page 47: ...Rev 3 00 Jan 25 2006 page xlv of lii Appendix Figure C 1 Package Dimensions TBP 112A 864...
Page 54: ...Rev 3 00 Jan 25 2006 page lii of lii...
Page 70: ...Section 1 Overview Rev 3 00 Jan 25 2006 page 16 of 872 REJ09B0286 0300...
Page 118: ...Section 3 MCU Operating Modes Rev 3 00 Jan 25 2006 page 64 of 872 REJ09B0286 0300...
Page 126: ...Section 4 Exception Handling Rev 3 00 Jan 25 2006 page 72 of 872 REJ09B0286 0300...
Page 198: ...Section 6 Bus Controller Rev 3 00 Jan 25 2006 page 144 of 872 REJ09B0286 0300...
Page 326: ...Section 10 8 Bit PWM Timer PWM Rev 3 00 Jan 25 2006 page 272 of 872 REJ09B0286 0300...
Page 440: ...Section 15 Watchdog Timer WDT Rev 3 00 Jan 25 2006 page 386 of 872 REJ09B0286 0300...
Page 606: ...Section 17 I 2 C Bus Interface IIC Rev 3 00 Jan 25 2006 page 552 of 872 REJ09B0286 0300...
Page 742: ...Section 19 Multimedia Card Interface MCIF Rev 3 00 Jan 25 2006 page 688 of 872 REJ09B0286 0300...
Page 750: ...Section 21 D A Converter Rev 3 00 Jan 25 2006 page 696 of 872 REJ09B0286 0300...
Page 768: ...Section 22 A D Converter Rev 3 00 Jan 25 2006 page 714 of 872 REJ09B0286 0300...
Page 770: ...Section 23 RAM Rev 3 00 Jan 25 2006 page 716 of 872 REJ09B0286 0300...
Page 824: ...Section 26 Clock Pulse Generator Rev 3 00 Jan 25 2006 page 770 of 872 REJ09B0286 0300...
Page 844: ...Section 27 Power Down Modes Rev 3 00 Jan 25 2006 page 790 of 872 REJ09B0286 0300...
Page 878: ...Section 28 List of Registers Rev 3 00 Jan 25 2006 page 824 of 872 REJ09B0286 0300...
Page 926: ...Index Rev 3 00 Jan 25 2006 page 872 of 872 REJ09B0286 0300...