Renesas H8S/2158, User Manual

Page: 232 / 929

Section 8 RAM-FIFO Unit (RFU)
Rev. 3.00 Jan 25, 2006 page 178 of 872
REJ09B0286-0300
8.2.13 Data Transfer ID Register (DTIDR)
DTIDR is a register provided in each pointer set. DTIDR selects the peripheral module, which is
an activation source of each pointer set.
A 4-bit ID has been assigned to the peripheral modules. DTIDR selects two IDs. The ID selected
by DTIDR is enabled by setting the IDE-A and IDE-B bits in DTCRA to 1.
When selecting an ID, the following two points should be noted:
•
To select two IDs, the IDs should be combined such that the data transfer direction is read and
write.
•
The same IDs should not be selected over several pointer sets.
Bit Bit Name Initial Value R/W Description
7
6
5
4 ID-A3
ID-A2
ID-A1
ID-A0 0
0
0
0 R/W
R/W
R/W
R/W ID-A Select
These bits write the ID number to be selected
by the IDE-A bit.
3
2
1
0 ID-B3
ID-B2
ID-B1
ID-B0 0
0
0
0 R/W
R/W
R/W
R/W ID-B Select
These bits write the ID number to be selected
by the IDE-B bit.
8.2.14 Data Transfer ID Read/Write Select Register A (DTIDSRA)
DTIDSRA selects the direction for transferring ID15 to ID8. As IDs have already been assigned
for the peripheral modules, the transfer direction is fixed. For details, refer to section 8.8,
Operation.
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0 IDRW15
IDRW14
IDRW13
IDRW12
IDRW11
IDRW10
IDRW9
IDRW8 0
0
0
0
0
0
0
0 R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W ID15 R/W to ID8 R/W
These bits select the direction for transferring
peripheral modules with ID numbers 15 to 8.
0: RAM
→
Peripheral modules (write)
1: Peripheral modules (read)
→
RAM