Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Jan 25, 2006 page 152 of 872
REJ09B0286-0300
7.3
Activation Sources
The DTC is activated by an interrupt request or by a write to DTVECR by software. The interrupt
request source to activate the DTC is selected by DTCER. At the end of a data transfer (or the last
consecutive transfer in the case of chain transfer), the interrupt flag that became the activation
source or the corresponding DTCER bit is cleared. The activation source flag, in the case of RXI0,
for example, is the RDRF flag in SCI_0.
When an interrupt has been designated as a DTC activation source, the existing CPU mask level
and interrupt controller priorities have no effect. If there is more than one activation source at the
same time, the DTC operates in accordance with the default priorities. Figure 7.2 shows a block
diagram of DTC activation source control. For details on the interrupt controller, see section 5,
Interrupt Controller.
CPU
DTC
DTCER
Source flag cleared
On-chip
peripheral
module
IRQ interrupt
Interrupt
request
Clear
Clear
controller
Clear request
Interrupt controller
Selection circuit
Interrupt mask
Select
DTVECR
Figure 7.2 Block Diagram of DTC Activation Source Control
Summary of Contents for H8S/2158
Page 10: ...Rev 3 00 Jan 25 2006 page viii of lii...
Page 36: ...Rev 3 00 Jan 25 2006 page xxxiv of lii B Product Lineup 863 C Package Dimensions 864 Index 865...
Page 47: ...Rev 3 00 Jan 25 2006 page xlv of lii Appendix Figure C 1 Package Dimensions TBP 112A 864...
Page 54: ...Rev 3 00 Jan 25 2006 page lii of lii...
Page 70: ...Section 1 Overview Rev 3 00 Jan 25 2006 page 16 of 872 REJ09B0286 0300...
Page 118: ...Section 3 MCU Operating Modes Rev 3 00 Jan 25 2006 page 64 of 872 REJ09B0286 0300...
Page 126: ...Section 4 Exception Handling Rev 3 00 Jan 25 2006 page 72 of 872 REJ09B0286 0300...
Page 198: ...Section 6 Bus Controller Rev 3 00 Jan 25 2006 page 144 of 872 REJ09B0286 0300...
Page 326: ...Section 10 8 Bit PWM Timer PWM Rev 3 00 Jan 25 2006 page 272 of 872 REJ09B0286 0300...
Page 440: ...Section 15 Watchdog Timer WDT Rev 3 00 Jan 25 2006 page 386 of 872 REJ09B0286 0300...
Page 606: ...Section 17 I 2 C Bus Interface IIC Rev 3 00 Jan 25 2006 page 552 of 872 REJ09B0286 0300...
Page 742: ...Section 19 Multimedia Card Interface MCIF Rev 3 00 Jan 25 2006 page 688 of 872 REJ09B0286 0300...
Page 750: ...Section 21 D A Converter Rev 3 00 Jan 25 2006 page 696 of 872 REJ09B0286 0300...
Page 768: ...Section 22 A D Converter Rev 3 00 Jan 25 2006 page 714 of 872 REJ09B0286 0300...
Page 770: ...Section 23 RAM Rev 3 00 Jan 25 2006 page 716 of 872 REJ09B0286 0300...
Page 824: ...Section 26 Clock Pulse Generator Rev 3 00 Jan 25 2006 page 770 of 872 REJ09B0286 0300...
Page 844: ...Section 27 Power Down Modes Rev 3 00 Jan 25 2006 page 790 of 872 REJ09B0286 0300...
Page 878: ...Section 28 List of Registers Rev 3 00 Jan 25 2006 page 824 of 872 REJ09B0286 0300...
Page 926: ...Index Rev 3 00 Jan 25 2006 page 872 of 872 REJ09B0286 0300...