Renesas H8S/2158, User Manual

Page: 224 / 929

Section 8 RAM-FIFO Unit (RFU)
Rev. 3.00 Jan 25, 2006 page 170 of 872
REJ09B0286-0300
8.2.2 Base Address Register (BAR)
BAR is a 16-bit register provided in each pointer set, and allocated to bits 19 to 4 in FSTR. The
base address should be set at the boundary specified by the BUD2 to BUD0 bits in DTCRA.
Otherwise, address specification by the pointer and status display by calculation inter-pointers
may not be performed correctly.
Bit Bit Name Initial Value R/W Description
31
to
20 — All 1 R Base Addresses 31 to 20
These bits are always read as 1 and cannot be
modified.
19
to
4 BA19
to
BA4 Undefined R/W Base Addresses 19 to 4
These bits specify a RAM base address that
can be used as the FIFO.
3
to
0 — All 0 R Base Addresses 3 to 0
These bits are always read as 0 and cannot be
modified.
8.2.3 Read Address Pointer (RAR)
RAR is an 11-bit pointer provided in each pointer set, and allocated to bits 10 to 0 in FSTR.
Bit Bit Name Initial Value R/W Description
31
to
11 — All 0 R Read Addresses 31 to 11
These bits are always read as 0 and cannot be
modified.
10
to
0 RA10
to
RA0 All 0 R/W Read Addresses 10 to 0
These bits are pointers to specify the RAM
address to be read from in a RAM read cycle of
the RFU. The RAM address is calculated by
BAR + RAR. These can be read as NRA. These
bits are incremented for the number of bytes to
be read for each RAM read cycle. However,
these bits are not incremented and cleared to 0
when exceeding the selected FIFO size.