Renesas H8S/2158, User Manual

Page: 829 / 929

Section 27 Power-Down Modes
Rev. 3.00 Jan 25, 2006 page 775 of 872
REJ09B0286-0300
Bit Bit Name Initial Value R/W Description
6 LSON 0 R/W Low-Speed On Flag
Specifies the operating mode to be entered after executing
the SLEEP instruction. This bit also controls whether to shift
to high-speed mode or subactive mode when watch mode
is cancelled.
When the SLEEP instruction is executed in high-speed
mode or medium-speed mode:
0: Shifts to sleep mode, software standby mode, or watch
mode
1: Shifts to watch mode or subactive mode
When the SLEEP instruction is executed in subactive
mode:
0: Shifts directly to watch mode or high-speed mode
1: Shifts to subsleep mode or watch mode
When watch mode is cancelled:
0: Shifts to high-speed mode
1: Shifts to subactive mode
5 NESEL 0 R/W Noise Elimination Sampling Frequency Select
Selects the frequency by which the subclock (
φ
SUB) input
from the EXCL pin is sampled using the clock (
φ
) generated
by the system clock pulse generator. Clear this bit to 0 in
this LSI.
0: Sampling using
φ
/32 clock
1: Sampling using
φ
/4 clock
4 EXCLE 0 R/W Subclock Input Enable
Enables/disables subclock input from the EXCL pin.
0: Disables subclock input from the EXCL pin
1: Enables subclock input from the EXCL pin
3 to 0
   
All 0 R/(W) Reserved
The initial value should not be changed.
27.1.3 System Control Register 2 (SYSCR2)
SYSCR2 controls switching of the system clock source. The system clock can be selected from the
clock (
φ
) input from the EXTAL and XTAL pins, the subclock (
φ
SUB) input from the EXCL pin,
or the 24-MHz clock (
φ
24) generated by the PLL circuit. SYSCR2 selects between
φ
and
φ
24.