Renesas H8S/2158, User Manual

Page: 697 / 929

Section 19 Multimedia Card Interface (MCIF)
Rev. 3.00 Jan 25, 2006 page 643 of 872
REJ09B0286-0300
For write data transmission, the contents of the command response and data response should be
analyzed, and then transmission should be triggered. In addition, the transfer clock (MCCLK)
output should be temporarily halted according to FIFO full/empty, and it should be resumed when
preparation has been completed.
For multiblock transfer in MMC mode, the command sequence should be temporarily halted for
every block break to select either to continue to the next block or to abort the multiblock transfer
command by issuing the CMD12 command, and then the command sequence should be resumed.
The transfer clock output is also halted while the command sequence is halted in a multiblock
read. To continue to the next block, the RD_CONTI and DATAEN bits should be set to 1. To
issue the CMD12 command, the CMDOFF bit should be set to 1 to abort the command sequence
on the MCIF side.
Any temporary halt of the transfer clock is determined one byte before the FIFO becomes
full/empty. The DATAEN bit should not be set to 1 when only one byte of data remains in the
transmit data FIFO. The receive data FIFO should be read when the FIFO becomes full, and the
RD_CONTI bit should be set to 1 after three bytes or more have been read.
19.3.10 Command Timeout Control Register (CTOCR)
CTOCR specifies the cycle to generate a timeout for the command response.
The counter (CTOUTC), to which the CPU does not have access, counts the transfer clock to
monitor the command timeout. The CTOUTC starts counting the transfer clock from the start of
command transmission. The CTOUTC stops counting the transfer clock when command response
reception has been completed, or when the command sequence has been aborted by setting the
CMDOFF bit to 1.
When the command response cannot be received, the CTOUTC continues counting the transfer
clock, and enters the command timeout error state when the number of transfer clock reaches the
number specified in CTOCR. When the CTERIE bit in INTCR1 is set to 1, the CTERI flag in
INTSTR1 is set. As the CTOUTC continues counting the transfer clock, the CTERI flag setting
condition is repeatedly generated. To perform command timeout error handling, the command
sequence should be aborted by setting the CMDOFF bit to 1, and then the CTERI flag should be
cleared to prevent extra-interrupt generation.