Renesas H8S/2158, User Manual

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Section 13 8-Bit Timer (TMR)
Rev. 3.00 Jan 25, 2006 page 342 of 872
REJ09B0286-0300
13.9.4 Conflict between Compare-Matches A and B
If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with
the priorities for the output states set for compare-match A and compare-match B, as shown in
table 13.5.
Table 13.5 Timer Output Priorities
Output Setting Priority
Toggle output High
1 output
0 output
No change Low
13.9.5 Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 13.6 shows the
relationship between the timing at which the internal clock is switched (by writing to the CKS1
and CKS0 bits) and the TCNT operation.
When the TCNT clock is generated from an internal clock, the falling edge of the internal clock
pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in
table 13.6, a TCNT clock pulse is generated on the assumption that the switchover is a falling
edge, and TCNT is incremented.
Erroneous incrementation can also happen when switching between internal and external clocks.