Section 14 Timer Connection
Rev. 3.00 Jan 25, 2006 page 365 of 872
REJ09B0286-0300
14.4.5
IVI Signal Fall Modification and IHI Synchronization
By using the timer connection facility and TMR_1, the fall of the IVI signal can be shifted
backward by the specified number of IHI signal waveforms. Also, the fall of the IVI signal can be
synchronized with the rise of the IHI signal.
To perform 8-bit timer divided waveform period measurement, TCNT in TMR_1 is set to count
external clock (IHI signal) pulses, and to be cleared on the rising edge of the external reset signal
(inverse of the IVI signal). The number of IHI signal pulses until the fall of the IVI signal is
written in TCORB.
Since the IVI signal supplied to the IVO signal selection circuit is normally set on the rise of the
IVI signal and reset on the fall, its waveform is the same as that of the original IVI signal. When
fall modification is selected, a reset is performed on a TMR_1 TCORB compare-match in TMR_1.
The fall of the waveform generated in this way can be synchronized with the rise of the IHI signal,
regardless of whether or not fall modification is selected.
Examples of TCR, TCSR, and TCORB settings in TMR_1 are shown in table 14.8, and the fall
modification/IHI synchronization timing chart is shown in figure 14.7.
Summary of Contents for H8S/2158
Page 10: ...Rev 3 00 Jan 25 2006 page viii of lii...
Page 36: ...Rev 3 00 Jan 25 2006 page xxxiv of lii B Product Lineup 863 C Package Dimensions 864 Index 865...
Page 47: ...Rev 3 00 Jan 25 2006 page xlv of lii Appendix Figure C 1 Package Dimensions TBP 112A 864...
Page 54: ...Rev 3 00 Jan 25 2006 page lii of lii...
Page 70: ...Section 1 Overview Rev 3 00 Jan 25 2006 page 16 of 872 REJ09B0286 0300...
Page 118: ...Section 3 MCU Operating Modes Rev 3 00 Jan 25 2006 page 64 of 872 REJ09B0286 0300...
Page 126: ...Section 4 Exception Handling Rev 3 00 Jan 25 2006 page 72 of 872 REJ09B0286 0300...
Page 198: ...Section 6 Bus Controller Rev 3 00 Jan 25 2006 page 144 of 872 REJ09B0286 0300...
Page 326: ...Section 10 8 Bit PWM Timer PWM Rev 3 00 Jan 25 2006 page 272 of 872 REJ09B0286 0300...
Page 440: ...Section 15 Watchdog Timer WDT Rev 3 00 Jan 25 2006 page 386 of 872 REJ09B0286 0300...
Page 606: ...Section 17 I 2 C Bus Interface IIC Rev 3 00 Jan 25 2006 page 552 of 872 REJ09B0286 0300...
Page 742: ...Section 19 Multimedia Card Interface MCIF Rev 3 00 Jan 25 2006 page 688 of 872 REJ09B0286 0300...
Page 750: ...Section 21 D A Converter Rev 3 00 Jan 25 2006 page 696 of 872 REJ09B0286 0300...
Page 768: ...Section 22 A D Converter Rev 3 00 Jan 25 2006 page 714 of 872 REJ09B0286 0300...
Page 770: ...Section 23 RAM Rev 3 00 Jan 25 2006 page 716 of 872 REJ09B0286 0300...
Page 824: ...Section 26 Clock Pulse Generator Rev 3 00 Jan 25 2006 page 770 of 872 REJ09B0286 0300...
Page 844: ...Section 27 Power Down Modes Rev 3 00 Jan 25 2006 page 790 of 872 REJ09B0286 0300...
Page 878: ...Section 28 List of Registers Rev 3 00 Jan 25 2006 page 824 of 872 REJ09B0286 0300...
Page 926: ...Index Rev 3 00 Jan 25 2006 page 872 of 872 REJ09B0286 0300...