Renesas H8S/2158, User Manual

Page: 163 / 929

Section 6 Bus Controller
Rev. 3.00 Jan 25, 2006 page 109 of 872
REJ09B0286-0300
Bit Bit Name Initial Value R/W Description
4 ASTCP 1 R/W CP/CF Expansion Area Access State Control
Selects the number of states for access to the CP/CF
expansion area when the CPCSE bit in BCR2 is set to
1. This bit also enables or disables wait-state insertion.
0: 2-state access space. Wait state insertion disabled in
CP/CF expansion area access
1: 3-state access space. Wait state insertion enabled in
CP/CF expansion area access
3 ADFULLE 0 R/W Address Output Full Enable
Controls the
IOS
signal output and address output in
access to the 256-kbyte expansion area and CP/CF
expansion area. For details, refer to section 9, I/O Ports.
2 EXCKS 0 R/W External Expansion Clock Select
Selects the operating clock used in external expansion
area access.
0: Medium-speed clock is selected as the operating
clock
1: System clock (
φ
) is selected as the operating clock.
The operating clock is switched in the bus cycle prior to
external expansion area access.
1 BUSDIVE 1 R/W Bus Division Arbitration Enable
Controls the bus arbitration timing for the divided bus
cycles in the RFU operation. For details, refer to section
8, RAM FIFO Unit (RFU).
0 CPCSE 0 R/W CP/CF Expansion Area Enable
Selects the expansion area to be accessed.
0: External address space (basic expansion area)
1: CP/CF expansion area (basic mode when CFE bit in
BCR is 0, memory card mode when CFE bit in BCR
is 1)