Renesas H8S/2158, User Manual

Page: 900 / 929

Section 29 Electrical Characteristics
Rev. 3.00 Jan 25, 2006 page 846 of 872
REJ09B0286-0300
Table 29.10 Timing of On-Chip Peripheral Modules (1)
Condition A: V
CC
= 3.0 V to 3.6 V, V
SS
= 0 V,
φ
= 32.768 kHz*, 5 MHz to 25 MHz
Condition B: V
CC
= 2.7 V to 3.6 V, V
SS
= 0 V,
φ
= 32.768 kHz*, 5 MHz to 20 MHz
Condition A Condition B
Item Symbol Min Max Min Max Unit
Test
Conditions
Output data delay time t
PWD
— 40 — 50
Input data setup time t
PRS
30 — 40 —
I/O ports
Input data hold time t
PRH
30 — 40 —
ns Figure 29.15
Timer output delay time t
FTOD
— 40 — 50
Timer input setup time t
FTIS
30 — 40 —
Figure 29.16
Timer clock input setup time t
FTCS
30 — 40 —
ns
Figure 29.17
Single edge t
FTCWH
1.5 — 1.5 —
FRT
Timer clock pulse
width
Both edges t
FTCWL
2.5 — 2.5 —
t
cyc
Timer output delay time t
TMOD
— 40 — 50 Figure 29.18
Timer reset input setup time t
TMRS
30 — 40 —
ns
Figure 29.20
Timer clock input setup time t
TMCS
30 — 40 — Figure 29.19
Single edge t
TMCWH
1.5 — 1.5 —
TMR
Timer clock pulse
width
Both edges t
TMCWL
2.5 — 2.5 —
t
cyc
PWM,
PWMX Pulse output delay time t
PWOD
— 40 — 50 ns Figure 29.21
Input clock cycle Asynchronous t
Scyc
4 — 4 —
Synchronous 6 — 6 —
t
cyc
Figure 29.22
Input clock pulse width t
SCKW
0.4 0.6 0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 1.5 — 1.5
Input clock fall time t
SCKf
— 1.5 — 1.5
t
cyc
Transmit data delay time
(synchronous)
t
TXD
— 40 — 50
Receive data setup time
(synchronous)
t
RXS
30 — 40 —
SCI
Receive data hold time
(synchronous) t
RXH
30 — 40 —
ns Figure 29.23
A/D
converter Trigger input setup time t
TRGS
30 — 40 — ns Figure 29.24
RESO
output delay time t
RESD
— 200 — 200 ns WDT
RESO
output pulse width t
RESOW
132 — 132 — t
cyc
Figure 29.25
Note:
*
Only the on-chip peripheral modules that can be used in subclock operation.