Renesas H8S/2158, User Manual

Page: 188 / 929

Section 6 Bus Controller
Rev. 3.00 Jan 25, 2006 page 134 of 872
REJ09B0286-0300
By program wait
T
1
Address bus
φ
AS
/
IOS *
(IOSE = 0)
RD
Data bus
Read data
Read
AS
/
IOS
(IOSE = 0)
CPCS1
(CPCSE = 1 and CFE = 0)
WR
Write data
Write
Notes:
↓
shown in
φ
clock indicates the
WAIT
/
CPWAIT
pin sampling timing.
* For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP/CF expansion area is accessed with CPCSE = 1.
WAIT
/
CPWAIT
Data bus
T
2
T
W
T
W
T
W
T
3
By
WAIT
/
CPWAIT
pin
Figure 6.13 Example of Wait State Insertion Timing (Pin Wait Mode)
6.6 Burst ROM Interface
In this LSI, the external address space can be designated as the burst ROM space by the BRSTRM
bit in BCR, and the burst ROM interface enabled. Consecutive burst accesses of a maximum four
or eight words can be performed only during CPU instruction fetch. 1 or 2 states can be selected
for burst ROM access.