Renesas H8S/2158, User Manual

Page: 202 / 929

Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Jan 25, 2006 page 148 of 872
REJ09B0286-0300
Bit Bit Name Initial Value R/W Description
0 Sz Undefined — DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
Legend:
X: Don't care
7.2.2 DTC Mode Register B (MRB)
MRB selects the DTC operating mode.
Bit Bit Name Initial Value R/W Description
7 CHNE Undefined — DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, see section 7.5.4, Chain
Transfer.
In data transfer with CHNE set to 1, determination of the
end of the specified number of data transfers, clearing
of the interrupt source flag, and clearing of DTCER are
not performed.
6 DISEL Undefined — DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time data transfer ends. When this bit
is cleared to 0, a CPU interrupt request is generated
only when the specified number of data transfer ends.
Note however that when the DTC is activated by a USB
or MCIF interrupt source and this bit is cleared to 0, this
LSI does not operate correctly. In such a case, be sure
to set this bit to 1.
5 to
0 — Undefined — Reserved
These bits have no effect on DTC operation. The write
value should always be 0.