Section 14 Timer Connection
Rev. 3.00 Jan 25, 2006 page 363 of 872
REJ09B0286-0300
IVI signal
IHI signal
divided
waveform
FRC
ICRB
ICRB(1)
ICRB(2)
ICRB(3)
ICRB(4)
Figure 14.5 Timing Chart for Measurement of IVI Signal and
IHI Signal Divided Waveform Periods
14.4.4
IHI Signal and 2fH Modification
By using the timer connection facility and FRT, even if there is a part of the IHI signal with twice
the frequency, this can be eliminated. In order for this function to operate properly, the duty cycle
of the IHI signal must be approximately 30% or less, or approximately 70% or above.
The 8-bit OCRDM contents or twice the OCRDM contents can be added automatically to the data
captured in ICRD in the FRT, and compare-matches generated at these points. The interval
between the two compare-matches is called a mask interval. A value equivalent to approximately
1/3 the IHI signal period is written in OCRDM. ICRD is set so that capture is performed on the
rise of the IHI signal.
Since the IHI signal supplied to the IHO signal selection circuit is normally set on the rise of the
IHI signal and reset on the fall, its waveform is the same as that of the original IHI signal. When
2fH modification is selected, IHI signal edge detection is disabled during mask intervals. Capture
is also disabled during these intervals.
Examples of TCR, TCSR, TOCR, and OCRDM settings in the FRT are shown in table 14.7, and
the 2fH modification timing chart is shown in figure 14.6.
Summary of Contents for H8S/2158
Page 10: ...Rev 3 00 Jan 25 2006 page viii of lii...
Page 36: ...Rev 3 00 Jan 25 2006 page xxxiv of lii B Product Lineup 863 C Package Dimensions 864 Index 865...
Page 47: ...Rev 3 00 Jan 25 2006 page xlv of lii Appendix Figure C 1 Package Dimensions TBP 112A 864...
Page 54: ...Rev 3 00 Jan 25 2006 page lii of lii...
Page 70: ...Section 1 Overview Rev 3 00 Jan 25 2006 page 16 of 872 REJ09B0286 0300...
Page 118: ...Section 3 MCU Operating Modes Rev 3 00 Jan 25 2006 page 64 of 872 REJ09B0286 0300...
Page 126: ...Section 4 Exception Handling Rev 3 00 Jan 25 2006 page 72 of 872 REJ09B0286 0300...
Page 198: ...Section 6 Bus Controller Rev 3 00 Jan 25 2006 page 144 of 872 REJ09B0286 0300...
Page 326: ...Section 10 8 Bit PWM Timer PWM Rev 3 00 Jan 25 2006 page 272 of 872 REJ09B0286 0300...
Page 440: ...Section 15 Watchdog Timer WDT Rev 3 00 Jan 25 2006 page 386 of 872 REJ09B0286 0300...
Page 606: ...Section 17 I 2 C Bus Interface IIC Rev 3 00 Jan 25 2006 page 552 of 872 REJ09B0286 0300...
Page 742: ...Section 19 Multimedia Card Interface MCIF Rev 3 00 Jan 25 2006 page 688 of 872 REJ09B0286 0300...
Page 750: ...Section 21 D A Converter Rev 3 00 Jan 25 2006 page 696 of 872 REJ09B0286 0300...
Page 768: ...Section 22 A D Converter Rev 3 00 Jan 25 2006 page 714 of 872 REJ09B0286 0300...
Page 770: ...Section 23 RAM Rev 3 00 Jan 25 2006 page 716 of 872 REJ09B0286 0300...
Page 824: ...Section 26 Clock Pulse Generator Rev 3 00 Jan 25 2006 page 770 of 872 REJ09B0286 0300...
Page 844: ...Section 27 Power Down Modes Rev 3 00 Jan 25 2006 page 790 of 872 REJ09B0286 0300...
Page 878: ...Section 28 List of Registers Rev 3 00 Jan 25 2006 page 824 of 872 REJ09B0286 0300...
Page 926: ...Index Rev 3 00 Jan 25 2006 page 872 of 872 REJ09B0286 0300...