Section 19 Multimedia Card Interface (MCIF)
Rev. 3.00 Jan 25, 2006 page 646 of 872
REJ09B0286-0300
Bit
Bit Name
Initial Value
R/W
Description
3
DTBUSY
0
R
Data Busy
Indicates command execution status. Indicates
that the MMC is in the busy state during or after
the command sequence of a command without
data transfer, which includes the busy state in
the response, or of a command with write data
has been ended.
0: Idle state waiting for a command, or
command sequence execution in progress
1: MMC indicates data busy after command
sequence ends.
2
DTBUSY_TU
—
R
Data Busy Pin Status
Monitors level of the MCDAT pin in MMC mode
or MCRxD pin in SPI mode.
This bit is monitored to confirm whether the
MMC is in busy state by deselecting the MMC in
busy state, and then selecting the MMC, again.
1
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
0
REQ
0
R
Interrupt Request
Indicates whether an interrupt is requested. An
interrupt request is the logical sum of the
INTSTR0 and INTSTR1 flags. The INTSTR0
and INTSTR1 flags are set by the enable bits in
INTCR0 and INTCR1.
0: No interrupts requested.
1: An interrupt is requested.
Summary of Contents for H8S/2158
Page 10: ...Rev 3 00 Jan 25 2006 page viii of lii...
Page 36: ...Rev 3 00 Jan 25 2006 page xxxiv of lii B Product Lineup 863 C Package Dimensions 864 Index 865...
Page 47: ...Rev 3 00 Jan 25 2006 page xlv of lii Appendix Figure C 1 Package Dimensions TBP 112A 864...
Page 54: ...Rev 3 00 Jan 25 2006 page lii of lii...
Page 70: ...Section 1 Overview Rev 3 00 Jan 25 2006 page 16 of 872 REJ09B0286 0300...
Page 118: ...Section 3 MCU Operating Modes Rev 3 00 Jan 25 2006 page 64 of 872 REJ09B0286 0300...
Page 126: ...Section 4 Exception Handling Rev 3 00 Jan 25 2006 page 72 of 872 REJ09B0286 0300...
Page 198: ...Section 6 Bus Controller Rev 3 00 Jan 25 2006 page 144 of 872 REJ09B0286 0300...
Page 326: ...Section 10 8 Bit PWM Timer PWM Rev 3 00 Jan 25 2006 page 272 of 872 REJ09B0286 0300...
Page 440: ...Section 15 Watchdog Timer WDT Rev 3 00 Jan 25 2006 page 386 of 872 REJ09B0286 0300...
Page 606: ...Section 17 I 2 C Bus Interface IIC Rev 3 00 Jan 25 2006 page 552 of 872 REJ09B0286 0300...
Page 742: ...Section 19 Multimedia Card Interface MCIF Rev 3 00 Jan 25 2006 page 688 of 872 REJ09B0286 0300...
Page 750: ...Section 21 D A Converter Rev 3 00 Jan 25 2006 page 696 of 872 REJ09B0286 0300...
Page 768: ...Section 22 A D Converter Rev 3 00 Jan 25 2006 page 714 of 872 REJ09B0286 0300...
Page 770: ...Section 23 RAM Rev 3 00 Jan 25 2006 page 716 of 872 REJ09B0286 0300...
Page 824: ...Section 26 Clock Pulse Generator Rev 3 00 Jan 25 2006 page 770 of 872 REJ09B0286 0300...
Page 844: ...Section 27 Power Down Modes Rev 3 00 Jan 25 2006 page 790 of 872 REJ09B0286 0300...
Page 878: ...Section 28 List of Registers Rev 3 00 Jan 25 2006 page 824 of 872 REJ09B0286 0300...
Page 926: ...Index Rev 3 00 Jan 25 2006 page 872 of 872 REJ09B0286 0300...