Renesas H8S/2158, User Manual

Page: 653 / 929

Section 18 Universal Serial Bus Interface (USB)
Rev. 3.00 Jan 25, 2006 page 599 of 872
REJ09B0286-0300
18.3.20 RFU/FIFO Read Request Flag Register (UDTRFR)
UDTRFR provides a flag indicating that endpoint 5 is placed in data transfer completion state.
Endpoint 5 has a 2-byte receive buffer in the USB module to temporarily store data received from
the host into the receive buffer before transferring it to the RAM-FIFO by the RFU.
The receive buffer holds the receive data until the RFU data transfer ends.
If the RAM-FIFO is full, the transaction may be completed normally even while receive data of
one or two bytes still remain in the receive buffer. At this time, the EP5TS bit in TSFR0 is not set
to 1 and the EP5UDTR bit is set to 1. By clearing the EP5UDTR bit to 0 when there is a space of
at least two bytes in the RAM-FIFO, data in the receive buffer is transferred to the RAM-FIFO,
and the EP5TS bit is set to 1 after transfer completes.
In the slave CPU, a space of at least two bytes must be secured in the RAM-FIFO and the
EP5UDTR bit must be cleared to 0 by an UDTR interrupt.
UDTRFR is initialized to H'00 by a system reset or function software reset (see section 18.3.16,
USB Control Registers 0 and 1 (USBCR0, USBCR1)).
Bit Bit Name Initial Value R/W Description
7 to 1 — All 0 R Reserved
These bits are always read as 0 and cannot be modified.
0 EP5UDTR 0 R/(W) Endpoint 5 RFU/FIFO Read Request Flag
0: Indicates that endpoint 5 receive buffer is empty
1: Indicates that endpoint 5 holds
[Clearing condition]
•
0 is written to EP5UDTR after EP5UDTR = 1 has
been read.
[Setting condition]
•
USB transfer has been completed normally while the
RAM-FIFO is full and the receive buffer holds data.