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Renesas H8S/2158, User Manual

The Renesas H8S/2158 is a versatile microcontroller with advanced features for embedded system design. Unlock the full potential of this product by downloading the User Manual for free from manualshive.com. This comprehensive manual provides in-depth guidance on programming, configuration, and troubleshooting, ensuring optimal performance.

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Section 6   Bus Controller

Rev. 3.00  Jan 25, 2006  page 143 of 872

REJ09B0286-0300

6.9.2

Bus Transfer Timing

When a bus request is received from a bus master with a higher priority than that of the bus master
that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. Each bus master can relinquish the bus at the timings given below.

CPU: 

The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or

RFU, the bus arbiter transfers the bus to the DTC.

•

 

DTC bus transfer timing

 

The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred
between the component operations. For details, refer to section 2.7, Bus States During
Instruction Execution in the H8S/2600 Series, H8S/2000 Series Programming Manual.

 

If the CPU is in sleep mode, the bus is transferred immediately.

•

 

RFU bus transfer timing

 

The bus is transferred at a break between bus cycles. Even in discrete operations, as in the
case of a longword-size access, the bus can be transferred between the component
operations. For details, refer to section 8, RAM-FIFO Unit (RFU).

 

If the CPU is in sleep mode, the bus is transferred immediately.

DTC: 

The DTC sends the bus arbiter a request for the bus when an activation request is generated.

Since the bus master priority of the DTC is lower than the RFU, the bus arbiter transfers the bus
mastership from the DTC to the RFU if the RFU requests the bus.

•

 

RFU bus transfer timing
The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the component operations. In addition, in 32-bit access by the DTC, the bus is not transferred
at a break between longword access cycles. For details, refer to section 8, RAM-FIFO Unit
(RFU).

RFU: 

The RFU has the highest bus master priority. The RFU sends the bus arbiter a request for

the bus when an activation request is generated. The RFU does not release the bus until it
completes its operation. For details, refer to section 8, RAM-FIFO Unit (RFU).

Summary of Contents for H8S/2158

Page 1: ...ok over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electron...

Page 2: ...t for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas...

Page 3: ...sas 16 Bit Single Chip Microcomputer H8S Family H8S 2100 Series H8S 2158 HD64F2158 The revision list can be viewed directly by clicking the title page The revision list summarizes the locations of rev...

Page 4: ...a total system before making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting f...

Page 5: ...ialization Note When power is first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on...

Page 6: ...nts 6 Overview 7 Description of Functional Modules CPU and System Control Modules On Chip Peripheral Modules The configuration of the functional description of each module differs according to the mod...

Page 7: ...the serial communication interface SCI has a smart card interface function Auxiliary hardware for encryption operation DES GF conforming to the Keitaide Music 2 standard is necessary to protect music...

Page 8: ...ntrol functions peripheral functions and electrical characteristics In order to understand the details of the CPU s functions Read the H8S 2600 Series H8S 2000 Series Programming Manual In order to un...

Page 9: ...s manuals for development tools Document Title Document No H8S H8 300 Series C C Compiler Assembler Optimizing Linkage Editor User s Manual REJ10B0058 H8S H8 300 Series Simulator Debugger User s Manua...

Page 10: ...Rev 3 00 Jan 25 2006 page viii of lii...

Page 11: ...erformed by means of IRQ sense port select register 16 ISSR16 and the IRQ sense port select register ISSR 6 3 1 Bus Control Register BCR 107 Bit table amended Bit Bit Name Initial Value R W Descriptio...

Page 12: ...tting of this condition should therefore be avoided Description of TMR_Y and TMR_X Cascaded Connection deleted 13 7 Input Capture Operation 336 Section number amended 13 9 6 Mode Setting with Cascaded...

Page 13: ...ays read as 0 and cannot be modified 16 7 8 Clock Output Control 455 Description amended At Transition from Smart Card Interface Mode to Software Standby Mode 1 Set the port data register DR At Transi...

Page 14: ...Figure 17 3 State Transitions of TDRE SDRF and RDRF Bits 507 Figure 17 3 amended b Receive mode Before TDRE After SDRE Before SDRF After RDRF 17 5 3 Master Receive Operation 520 Description amended 9...

Page 15: ...bit is cleared between the 7th clock fall and the 8th clock fall the IRIC flag clear data will be retained internally Therefore the WAIT State will be cancelled right after WAIT insertion on 8th cloc...

Page 16: ...or subsequent frame take avoidance measures S SLA R W S SLA R W A DATA2 S SLA R W A SLA R W A DATA3 A DATA4 DATA1 I2C bus interface Master transmit mode Transmit data match Transmit timing match Rece...

Page 17: ...eviation Number of Bits Address Module Data Bus Width Number of Access States Command register 5 CMDR5 8 H FBC5 MCIF 8 3 mand start register CMDSTRT 8 H FBC6 MCIF 8 3 Operation control register OPCR 8...

Page 18: ...alized Initialized Initializ MCIF ed PSPRD Initialized Initialized Initialized Initialized Initialized Initialized Initialized DTOUTRH Initialized Initialized Initialized Initialized Initialized Initi...

Page 19: ...m Counter PC 27 2 4 3 Extended Control Register EXR 27 2 4 4 Condition Code Register CCR 28 2 4 5 Initial Register Values 29 2 5 Data Formats 30 2 5 1 General Register Data Formats 30 2 5 2 Memory Dat...

Page 20: ...n Handling 65 4 1 Exception Handling Types and Priority 65 4 2 Exception Sources and Exception Vector Table 66 4 3 Reset 67 4 3 1 Reset Exception Handling 68 4 3 2 Interrupts after Reset 69 4 3 3 On C...

Page 21: ...tructions that Disable Interrupts 102 5 7 3 Interrupts during Execution of EEPMOV Instruction 102 Section 6 Bus Controller 103 6 1 Features 103 6 2 Input Output Pins 105 6 3 Register Descriptions 106...

Page 22: ...ECR 151 7 3 Activation Sources 152 7 4 Location of Register Information and DTC Vector Table 153 7 5 Operation 156 7 5 1 Normal Mode 157 7 5 2 Repeat Mode 158 7 5 3 Block Transfer Mode 159 7 5 4 Chain...

Page 23: ...fer ID Read Write Select Register B DTIDSRB 179 8 2 16 Data Transfer Status Register A DTSTRA 179 8 2 17 Data Transfer Status Register B DTSTRB 180 8 2 18 Data Transfer Control Register C DTCRC 180 8...

Page 24: ...Pull Up MOS Control Register P3PCR 217 9 3 4 Pin Functions 217 9 3 5 Port 3 Input Pull Up MOS 222 9 4 Port 4 222 9 4 1 Port 4 Data Direction Register P4DDR 223 9 4 2 Port 4 Data Register P4DR 223 9 4...

Page 25: ...ister Descriptions 263 10 3 1 PWM Register Select PWSL 264 10 3 2 PWM Data Registers PWDR0 to PWDR15 266 10 3 3 PWM Data Polarity Registers A and B PWDPRA and PWDPRB 266 10 3 4 PWM Output Enable Regis...

Page 26: ...etting 304 12 5 7 Timing of Output Compare Flag OCF setting 305 12 5 8 Timing of FRC Overflow Flag Setting 305 12 5 9 Automatic Addition Timing 306 12 5 10 Mask Signal Generation Timing 307 12 6 Inter...

Page 27: ...ompare Match 341 13 9 4 Conflict between Compare Matches A and B 342 13 9 5 Switching of Internal Clocks and TCNT Operation 342 13 9 6 Mode Setting with Cascaded Connection 344 Section 14 Timer Connec...

Page 28: ...d Sub Active and Watch Modes 385 Section 16 Serial Communication Interface SCI IrDA and CRC 387 16 1 Features 387 16 2 Input Output Pins 391 16 3 Register Descriptions 391 16 3 1 Receive Shift Registe...

Page 29: ...16 7 3 Block Transfer Mode 447 16 7 4 Receive Data Sampling Timing and Reception Margin 447 16 7 5 Initialization 449 16 7 6 Serial Data Transmission Except in Block Transfer Mode 450 16 7 7 Serial D...

Page 30: ...11 IIC Operation Reservation Adapter Data Register ICDRX 507 17 3 12 IIC Data Shift Register ICDRS 508 17 3 13 IIC Operation Reservation Adapter Count Register ICCNT 508 17 3 14 IIC Operation Reservat...

Page 31: ...r DEVRSMR 589 18 3 15 Interrupt Source Select Register 0 INTSELR0 590 18 3 16 USB Control Registers 0 and 1 USBCR0 USBCR1 592 18 3 17 USB PLL Control Register UPLLCR 595 18 3 18 Configuration Value Re...

Page 32: ...3 16 Transfer Clock Control Register CLKON 654 19 4 MCIF Activation 655 19 4 1 Initial Status 655 19 4 2 Activation Procedure 655 19 5 Operations in MMC Mode 656 19 5 1 Operation of Broadcast Commands...

Page 33: ...D Conversion Accuracy Definitions 709 22 8 Usage Notes 711 22 8 1 Permissible Signal Source Impedance 711 22 8 2 Influences on Absolute Accuracy 711 22 8 3 Setting Range of Analog Power Supply and Ot...

Page 34: ...ndary Scan Register SDBSR 746 25 3 4 ID Code Register SDIDR 754 25 4 Operation 755 25 4 1 TAP Controller State Transitions 755 25 4 2 H UDI Reset 755 25 5 Boundary Scan 756 25 5 1 Supported Instructio...

Page 35: ...10 Module Stop Mode 787 27 11 Direct Transitions 788 27 12 Usage Notes 789 27 12 1 I O Port Status 789 27 12 2 Current Consumption when Waiting for Oscillation Stabilization 789 27 12 3 DTC Module St...

Page 36: ...Rev 3 00 Jan 25 2006 page xxxiv of lii B Product Lineup 863 C Package Dimensions 864 Index 865...

Page 37: ...ats Examples 44 Figure 2 12 Branch Address Specification in Memory Indirect Addressing Mode 47 Figure 2 13 State Transitions 51 Section 3 MCU Operating Modes Figure 3 1 Address Map Mode 2 62 Figure 3...

Page 38: ...3 State Access Space Odd Byte Access 131 Figure 6 12 Bus Timing for 16 Bit 3 State Access Space Word Access 132 Figure 6 13 Example of Wait State Insertion Timing Pin Wait Mode 134 Figure 6 14 Access...

Page 39: ...Flow 203 Section 10 8 Bit PWM Timer PWM Figure 10 1 Block Diagram of PWM Timer 262 Figure 10 2 Example of Additional Pulse Timing When Upper 4 Bits of PWDR B 1000 271 Section 11 14 Bit PWM Timer PWMX...

Page 40: ...Output Example 330 Figure 13 4 Count Timing for Internal Clock Input 331 Figure 13 5 Count Timing for External Clock Input 331 Figure 13 6 Timing of CMF Setting at Compare Match 332 Figure 13 7 Timin...

Page 41: ...nchronous Mode 419 Figure 16 5 Relation between Output Clock and Transmit Data Phase Asynchronous Mode 420 Figure 16 6 Basic Clock Examples When Average Transfer Rate Is Selected 1 422 Figure 16 7 Bas...

Page 42: ...re 16 34 Clock Output Fixing Timing 455 Figure 16 35 Clock Stop and Restart Procedure 456 Figure 16 36 IrDA Block Diagram 456 Figure 16 37 IrDA Transmission and Reception 457 Figure 16 38 Sample Trans...

Page 43: ...9 Figure 17 22 Notes on Reading Master Receive Data 544 Figure 17 23 Flowchart and Timing of Start Condition Issuance for Retransmission 545 Figure 17 24 Stop Condition Issuance Timing 546 Figure 17 2...

Page 44: ...Read Data 2 665 Figure 19 9 Example of Command Sequence for Commands with Read Data 3 666 Figure 19 10 Example of Command Sequence for Commands with Read Data 4 667 Figure 19 11 Operational Flow for C...

Page 45: ...ID Code Area 731 Figure 24 8 Programming Erasing Flowchart Example in User Program Mode 732 Figure 24 9 Program Program Verify Flowchart 734 Figure 24 10 Erase Erase Verify Flowchart 736 Figure 24 11...

Page 46: ...29 11 Basic Bus Timing 3 State Access with One Wait State 842 Figure 29 12 CF Interface Basic Timing 3 State Access 843 Figure 29 13 Burst ROM Access Timing 2 State Access 844 Figure 29 14 Burst ROM...

Page 47: ...Rev 3 00 Jan 25 2006 page xlv of lii Appendix Figure C 1 Package Dimensions TBP 112A 864...

Page 48: ...ble 2 11 Addressing Modes 45 Table 2 12 Absolute Address Access Ranges 46 Table 2 13 Effective Address Calculation 1 48 Table 2 13 Effective Address Calculation 2 49 Section 3 MCU Operating Modes Tabl...

Page 49: ...es Used and Valid Strobes 138 Table 6 11 Pin States in Idle Cycle 142 Section 7 Data Transfer Controller DTC Table 7 1 Correspondence between Interrupt Sources and DTCER 150 Table 7 2 Interrupt Source...

Page 50: ...2 16 Bit Free Running Timer FRT Table 12 1 Pin Configuration 289 Table 12 2 FRT Interrupt Sources 308 Table 12 3 Switching of Internal Clock and FRC Operation 313 Section 13 8 Bit Timer TMR Table 13 1...

Page 51: ...Rates Smart Card Interface Mode n 0 s 372 411 Table 16 9 Maximum Bit Rate for Each Frequency Smart Card Interface Mode S 372 411 Table 16 10 Serial Transfer Formats Asynchronous Mode 418 Table 16 11...

Page 52: ...Table 19 4 Correspondence between Number of Command Response Bytes and RSPR Register 639 Table 19 5 Card States in which Command Sequence Is Halted 642 Table 19 6 MCIF Interrupt Sources 687 Section 2...

Page 53: ...m Ratings 825 Table 29 2 DC Characteristics 1 826 Table 29 2 DC Characteristics 2 828 Table 29 2 DC Characteristics 3 829 Table 29 3 Permissible Output Currents 830 Table 29 4 I2 C Bus Drive Character...

Page 54: ...Rev 3 00 Jan 25 2006 page lii of lii...

Page 55: ...mer PWM 14 bit PWM timer PWMX 16 bit free running timer FRT 8 bit timer TMR Timer connection Watchdog timer WDT Asynchronous or clocked synchronous serial communication interface SCI CRC operator CRC...

Page 56: ...MCTxD P32 D10 CPD10 WUE10 MCDAT MCRxD P33 D11 CPD11 WUE11 MCDATDIR MCCSA P34 D12 CPD12 WUE12 MCCMDDIR MCCSB P35 D13 CPD13 WUE13 P36 D14 CPD14 WUE14 P37 D15 CPD15 WUE15 P50 IRQ8 TxD0 P51 IRQ9 RxD0 P52...

Page 57: ...J9 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 X1 X2 VCL STBY VSS ETMS P20 A8 PW8 CPA8 P21 A9 PW9 CPA9 P51 IRQ9 RxD0 P50 IRQ8 TxD0 ETRST VSS P22 A10 PW10 CPA10 P25 A1...

Page 58: ...MD2 MD2 VCC D3 MD1 MD1 VSS D2 MD0 MD0 VSS D1 NMI NMI FA9 E4 STBY STBY VCC E3 VCL VCL VCL E1 X1 X1 NC E2 X2 X2 NC F3 ETRST ETRST VSS F1 P51 IRQ9 RxD0 P51 IRQ9 RxD0 FA17 F2 P50 IRQ8 TxD0 P50 IRQ8 TxD0...

Page 59: ...P65 FTID CIN5 KIN5 CSYNCI 1 D5 CPD5 2 P65 FTID CIN5 KIN5 CSYNCI XVERDATA NC H5 P66 FTOB CIN6 KIN6 CBLANK 1 D6 CPD6 2 P66 FTOB CIN6 KIN6 CBLANK DMNS NC J5 P67 CIN7 KIN7 1 D7 CPD7 2 P67 CIN7 KIN7 DPLS...

Page 60: ...1 ExMCDATDIR ExMCCSA HSYNCO NC J11 P44 IRQ4 TMIX ExMCCMDDIR ExMCCSB P44 IRQ4 TMIX ExMCCMDDIR ExMCCSB NC H9 P45 IRQ5 TMIY P45 IRQ5 TMIY NC H10 P46 IRQ6 TMOX P46 IRQ6 TMOX NC H11 P47 IRQ7 TMOY P47 IRQ7...

Page 61: ...WUE10 MCDAT MCRxD FO2 A7 D11 CPD11 P33 WUE11 MCDATDIR MCCSA FO3 B7 D12 CPD12 P34 WUE12 MCCMDDIR MCCSB FO4 C6 D13 CPD13 P35 WUE13 FO5 A6 D14 CPD14 P36 WUE14 FO6 B6 D15 CPD15 P37 WUE15 FO7 D6 P85 ExIRQ...

Page 62: ...ction see section 26 Clock Pulse Generator G3 Output Supplies the system clock to external devices EXCL G3 Input 32 768 kHz external clock for subclock should be supplied X1 E1 Input Clock X2 E2 Input...

Page 63: ...bus D7 to D0 J5 H5 L4 K4 K3 H4 L2 K2 Lower bidirectional data bus CPREG CPA10 to CPA0 F10 F8 E11 E10 D9 C10 B11 C9 B10 A10 D8 B9 Output CompactFlash address output pins CPD15 to CPD0 B6 A6 C6 B7 A7 C...

Page 64: ...the external space is being written to and the lower half of the data bus is enabled AS IOS H1 Output This pin is low when address output on the address bus is valid CS256 G2 Output Indicates that the...

Page 65: ...RT FTIA to FTID H4 K3 K4 L4 Input Input capture input pins TMO0 TMO1 TMOX TMOY H8 J10 H10 H11 Output Waveform output pins with output compare function 8 bit timer TMR_0 TMR_1 TMR_X TMR_Y TMI0 TMI1 TMI...

Page 66: ...open drain output I 2 C bus interface IIC SDA0 SDA1 D5 A3 Input Output IIC data input output pins These pins can drive a bus directly with the NMOS open drain output KIN9 to KIN0 J8 K9 J5 H5 L4 K4 K3...

Page 67: ...should be connected to the system power supply A D converter D A converter AVSS K8 L9 Input Ground pins for the A D converter and D A converter These pins should be connected to the system power supp...

Page 68: ...nput Output Command output response input pins in MMC mode ExMCDAT MCDAT H8 C7 Input Output Data I O pins in MMC mode Multimedia card interface MCIF ExMCDATDIR ExMCCMDDIR MCDATDIR MCCMDDIR J10 J11 A7...

Page 69: ...t Output Eight input output pins P77 to P72 H7 L8 J7 K7 L7 H6 Input Six input pins P87 to P80 A9 C8 D6 A5 A3 B4 D5 A4 Input Output Eight input output pins P97 to P90 G2 G3 H1 G4 H3 J2 K1 J3 Input Outp...

Page 70: ...Section 1 Overview Rev 3 00 Jan 25 2006 page 16 of 872 REJ09B0286 0300...

Page 71: ...t general registers also usable as sixteen 8 bit registers or eight 32 bit registers Sixty five basic instructions 8 16 32 bit arithmetic and logic instructions Multiply and divide instructions Powerf...

Page 72: ...ifferences between the H8S 2600 CPU and the H8S 2000 CPU are as shown below Register configuration The MAC register is supported only by the H8S 2600 CPU Basic instructions The four instructions MAC C...

Page 73: ...ctions have been enhanced Signed multiply and divide instructions have been added Two bit shift and two bit rotate instructions have been added Instructions for saving and restoring multiple registers...

Page 74: ...set All instructions and addressing modes can be used Only the lower 16 bits of effective addresses EA are valid Exception vector table and memory indirect branch addresses In normal mode the top are...

Page 75: ...000A H 000B Reset exception vector Reserved for system use Exception vector 1 Exception vector 2 Exception vector table Reserved for system use Figure 2 1 Exception Vector Table Normal Mode a Subrout...

Page 76: ...ctor table and memory indirect branch addresses In advanced mode the top area starting at H 00000000 is allocated to the exception vector table in 32 bit units In each 32 bits the upper 8 bits are ign...

Page 77: ...as H 00 Branch addresses can be stored in the area from H 00000000 to H 000000FF Note that the top area of this range is also used for the exception vector table Stack structure In advanced mode when...

Page 78: ...ess space in normal mode and a maximum 16 Mbyte architecturally 4 Gbyte address space in advanced mode The usable modes and address spaces differ depending on the product For details on each product s...

Page 79: ...15 0 7 0 7 0 E0 E1 E2 E3 E4 E5 E6 E7 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L SP PC EXR T I2 to I0 CCR I UI Stack pointer Program counter Extended control register Trace bit In...

Page 80: ...These registers are functionally equivalent providing a maximum sixteen 16 bit registers The E registers E0 to E7 are also referred to as extended registers When the general registers are used as 8 b...

Page 81: ...tes one word so the least significant PC bit is ignored When an instruction is fetched for read the least significant PC bit is regarded as 0 2 4 3 Extended Control Register EXR EXR does not affect op...

Page 82: ...W User Bit or Interrupt Mask Bit Can be written to and read from by software using the LDC STC ANDC ORC and XORC instructions 5 H Undefined R W Half Carry Flag When the ADD B ADDX B SUB B SUBX B CMP B...

Page 83: ...dicate a borrow Shift and rotate instructions to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions 2 4 5 Initial Register Values Reset exception handli...

Page 84: ...djust instructions treat byte data as two digits of 4 bit BCD data 2 5 1 General Register Data Formats Figure 2 9 shows the data formats of general registers 7 0 7 0 MSB LSB MSB LSB 7 0 4 3 Don t care...

Page 85: ...LSB En Rn ERn En Rn RnH RnL MSB LSB General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Data Type Data Image Re...

Page 86: ...o address error occurs but the least significant bit of the address is regarded as 0 so the access starts at the preceding address This also applies to instruction fetches When SP ER7 is used as an ad...

Page 87: ...ND OR XOR NOT B W L 4 Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B W L 8 Bit manipulation BSET BCLR BNOT BTST BLD BILD BST BIST BAND BIAND BOR BIOR BXOR BIXOR B 14 Branch BCC 4 JMP BSR JSR RTS 5...

Page 88: ...al register 32 bit register EAd Destination operand EAs Source operand EXR Extended control register CCR Condition code register N N negative flag in CCR Z Z zero flag in CCR V V overflow flag in CCR...

Page 89: ...ral register from the stack POP W Rn is identical to MOV W SP Rn POP L ERn is identical to MOV L SP ERn PUSH W L Rn SP Pushes a general register onto the stack PUSH W Rn is identical to MOV W Rn SP PU...

Page 90: ...register Only the value 1 can be added to or subtracted from byte operands ADDS SUBS L Rd 1 Rd Rd 2 Rd Rd 4 Rd Adds or subtracts the value 1 2 or 4 to or from data in a 32 bit register DAA DAS B Rd d...

Page 91: ...sets the CCR bits according to the result NEG B W L 0 Rd Rd Takes the two s complement arithmetic complement of data in a general register EXTU W L Rd zero extension Rd Extends the lower 8 bits of a...

Page 92: ...OT B W L Rd Rd Takes the one s complement logical complement of data in a general register Note Size refers to the operand size B Byte W Word L Longword Table 2 6 Shift Instructions Instruction Size F...

Page 93: ...egister or memory operand and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower three bits of a general register BAND B C bit No of EAd C Logically...

Page 94: ...flag The bit number is specified by 3 bit immediate data BLD B bit No of EAd C Transfers a specified bit in a general register or memory operand to the carry flag BILD B bit No of EAd C Transfers the...

Page 95: ...r false Never BHI High C Z 0 BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N...

Page 96: ...een them and memory The upper 8 bits are valid STC B W CCR EAd EXR EAd Transfers CCR or EXR contents to a general register or memory operand Although CCR and EXR are 8 bit registers word size transfer...

Page 97: ...nstruction consists of an operation field op a register field r an effective address extension EA and a condition field cc Figure 2 11 shows examples of instruction formats Operation field Indicates t...

Page 98: ...ive Address Calculation The H8S 2000 CPU supports the eight addressing modes listed in table 2 11 Each instruction uses a subset of these addressing modes Arithmetic and logic operations instructions...

Page 99: ...address register ERn which contains the address of a memory operand If the address is a program instruction address the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 H 00 2 7 3...

Page 100: ...address the upper 16 bits are all assumed to be 1 H FFFF For a 16 bit absolute address the upper 16 bits are a sign extension For a 32 bit absolute address the entire address space is accessed A 24 bi...

Page 101: ...ifying a memory operand which contains a branch address The upper bits of the 8 bit absolute address are all assumed to be 0 so the address range is 0 to 255 H 0000 to H 00FF in normal mode H 000000 t...

Page 102: ...Rn 4 r op disp r op rm op rn 31 0 31 0 r op Don t care 31 23 31 0 Don t care 31 0 disp 31 0 31 0 31 23 31 0 Don t care 31 23 31 0 Don t care 24 24 24 24 Addressing Mode and Instruction Format Effectiv...

Page 103: ...24 24 24 24 Addressing Mode and Instruction Format Absolute address Immediate Effective Address Calculation Effective Address EA Sign extension Operand is immediate data 31 23 7 Program counter relati...

Page 104: ...ng state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source such as a reset trace interrupt or trap instruction The CPU fetches a start address...

Page 105: ...ate occurs whenever RES goes low A transition can also be made to the reset state when the watchdog timer overflows From any state a transition to hardware standby mode occurs when STBY goes low The p...

Page 106: ...uctions in cases where a register containing a write only bit is used or a bit is directly manipulated for a port because this may rewrite data of a bit other than the bit to be manipulated Example Th...

Page 107: ...DR 1 1 1 1 1 1 1 0 DR 1 0 0 0 0 0 0 0 Description on Operation 1 When the BCLR instruction is executed first the CPU reads P4DDR Since P4DDR is a write only register so the CPU reads H FF In this exam...

Page 108: ...dress indicated by ER5 to the address indicated by ER6 ER6 ER6 R4 1 ER5 ER5 R4 1 2 Set R4 1 and ER6 so that the end address of the destination address value of ER6 R4 1 does not exceed H 00FFFFFF 2 th...

Page 109: ...tch to extended mode by setting bit EXPE in MDCR to 1 Modes 0 1 and 5 cannot be used in this LSI Modes 4 6 and 7 are specific modes Thus mode pins should be set to enable mode 2 or 3 in normal program...

Page 110: ...Extended mode 6 to 3 All 0 R Reserved 2 1 0 MDS2 MDS1 MDS0 R R R Mode Select 2 to 0 These bits indicate the input levels at mode pins MD2 MD1 and MD0 the current operating mode Bits MDS2 MDS1 and MDS...

Page 111: ...hen a specified address of addresses H F80000 to H FBFFFF is accessed 6 IOSE 0 R W IOS Enable Enables or disables AS IOS pin function in extended mode 0 AS pin Outputs low when an external area is acc...

Page 112: ...e KINn pin registers TCR_X TCR_Y TCSR_X TCSR_Y TICRR TCORA_Y TICRF TCORB_Y TCNT_X TCNT_Y TCORC TISR TCORA_X TCORB_X of 8 bit timers TMR_X TMR_Y and timer connection registers TCONRI TCONRO TCONRS SEDG...

Page 113: ...IIC_0 and the IICX1 bit controls IIC_1 4 IICE 0 R W IIC Master Enable Enables or disables CPU access for IIC registers ICCR ICSR ICDR SARX ICMR SAR PWMX registers DADRAH DACR DADRAL DADRBH DACNTH DADR...

Page 114: ...the timer counter TCNT and a count condition together with bits CKS2 to CKS0 in the timer control register TCR For details see section 13 3 4 Timer Control Register TCR 3 3 Operating Mode Descriptions...

Page 115: ...ions as a data bus when the ABW bit in WSCR is cleared to 0 3 3 3 Pin Functions Pin functions of ports 1 to 3 6 9 and A depend on the operating mode Table 3 2 shows pin functions in each operating mod...

Page 116: ...rea Reserved area On chip RAM 6 144 bytes External address space CP CF expansion area External address space On chip RAM 3 968 bytes 1 2 1 2 1 2 1 2 Internal I O registers 3 On chip RAM 3 968 bytes Re...

Page 117: ...On chip ROM ROM 56 kbytes RAM 4 kbytes Mode 3 EXPE 1 Normal mode Extended mode with on chip ROM Internal I O registers 2 On chip RAM Internal I O registers 1 H EFFF H E080 H FEFF H FFFF H FE40 H FF7F...

Page 118: ...Section 3 MCU Operating Modes Rev 3 00 Jan 25 2006 page 64 of 872 REJ09B0286 0300...

Page 119: ...e Start of Exception Handling High Reset Starts immediately after a low to high transition of the RES pin or when the watchdog timer overflows Interrupt Starts when execution of the current instructio...

Page 120: ...000027 10 H 0014 to H 0015 H 000028 to H 00002B Trap instruction four sources 11 H 0016 to H 0017 H 00002C to H 00002F Direct transition clock switchover 12 H 0018 to H 0019 H 000030 to H 000033 Rese...

Page 121: ...H 0000EF External interrupt IRQ12 60 H 0078 to H 0079 H 0000F0 to H 0000F3 External interrupt IRQ13 61 H 007A to H 007B H 0000F4 to H 0000F7 External interrupt IRQ14 62 H 007C to H 007D H 0000F8 to H...

Page 122: ...2 The reset exception handling vector address is read and transferred to the PC and program execution starts from the address indicated by the PC Figure 4 1 shows an example of the reset sequence RES...

Page 123: ...he interrupt controller The sources to start interrupt exception handling are external interrupt sources NMI IRQ15 to IRQ0 KIN9 to KIN0 and WUE15 to WUE8 and internal interrupt sources from the on chi...

Page 124: ...p instruction exception handling Table 4 3 Status of CCR after Trap Instruction Exception Handling CCR Interrupt Control Mode I UI 0 Set to 1 Retains value prior to execution 1 Set to 1 Set to 1 4 6 S...

Page 125: ...ng instructions to restore registers POP W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Setting SP to an odd value may lead to a malfunction Figure 4 3 shows an example of what happens when the SP valu...

Page 126: ...Section 4 Exception Handling Rev 3 00 Jan 25 2006 page 72 of 872 REJ09B0286 0300...

Page 127: ...ule for all interrupts except NMI KIN and WUE Independent vector addresses All interrupt sources are assigned independent vector addresses making it unnecessary for the source to be identified in the...

Page 128: ...WUE input ISCR IER KMIMR WUEMR ICR Interrupt controller Priority level determination Interrupt request Vector number I UI CCR CPU ICR ISCR IER ISR KMIMR WUEMR SYSCR Interrupt control register IRQ sen...

Page 129: ...ested at falling edge WUE15 to WUE8 Input Maskable external interrupts An interrupt is requested at falling edge 5 3 Register Descriptions The interrupt controller has the following registers For deta...

Page 130: ...R W Interrupt Control Level 0 Corresponding interrupt source is interrupt control level 0 no priority 1 Corresponding interrupt source is interrupt control level 1 priority Note n A to D Table 5 2 Co...

Page 131: ...Undefined R W Condition Match Flag Address break source flag Indicates that an address specified by BARA to BARC is prefetched Clearing condition When an exception handling is executed for an address...

Page 132: ...ame Initial Value R W Description 7 to 0 A23 to A16 All 0 R W Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus BARB Bit Bit Name Initial Value R W Descri...

Page 133: ...ense Control A 00 Interrupt request generated at low level of IRQn or ExIRQn input 01 Interrupt request generated at falling edge of IRQn or ExIRQn input 10 Interrupt request generated at rising edge...

Page 134: ...of IRQn or ExIRQn input 11 Interrupt request generated at both falling and rising edges of IRQn or ExIRQn input n 7 to 4 ISCRL Bit Bit Name Initial Value R W Description 7 6 IRQ3SCB IRQ3SCA 0 0 R W R...

Page 135: ...on 15 14 13 12 11 10 9 8 IRQ15E IRQ14E IRQ13E IRQ12E IRQ11E IRQ10E IRQ9E IRQ8E 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W IRQn Enable n 15 to 8 The IRQn interrupt request is enabled when this bit...

Page 136: ...ed when low level detection is set and IRQn or ExIRQn input is high n 15 to 8 When IRQn interrupt exception handling is executed when falling edge rising edge or both edge detection is set ISR Bit Bit...

Page 137: ...interrupt request 1 Disables a key sensing input interrupt request KMIMR6 Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 KMIM7 KMIM6 KMIM5 KMIM4 KMIM3 KMIM2 KMIM1 KMIM0 1 1 1 1 1 1 1 1 R W...

Page 138: ...pins ExIRQ15 to ExIRQ2 Interrupts IRQ15 to IRQ0 have the following features The interrupt exception handling for interrupt requests IRQ15 to IRQ0 can be started at an independent vector address Using...

Page 139: ...ion handling for an interrupt request from the same group is started at the same vector address Enabling or disabling of interrupt requests can be selected with the I bit in CCR An interrupt is genera...

Page 140: ...interrupt can be set by ICR The DTC can be activated by an interrupt request from an on chip peripheral module An interrupt request that activates the DTC is not affected by the interrupt control mod...

Page 141: ...WOVI1 Interval timer 26 H 0034 H 000068 ICRA0 Address break 27 H 0036 H 00006C A D converter ADI A D conversion end 28 H 0038 H 000070 ICRB7 Reserved for system use 29 H 003A H 000074 External pin KI...

Page 142: ...Compare match A OVI0 Overflow Reserved for system use 64 65 66 67 H 0080 H 0082 H 0084 H 0086 H 000100 H 000104 H 000108 H 00010C ICRB3 TMR_1 CMIA1 Compare match A CMIB1 Compare match B OVI1 Overflow...

Page 143: ...3 94 95 H 00B8 H 00BA H 00BC H 00BE H 000170 H 000174 H 000178 H 00017C ICRC4 IIC_1 IICC1 IICM1 IICR1 IICT1 96 97 98 99 H 00C0 H 00C2 H 00C4 H 00C6 H 000180 H 000184 H 000188 H 00018C ICRC3 Reserved f...

Page 144: ...Table 5 4 shows the interrupt control modes Table 5 4 Interrupt Control Modes SYSCR Interrupt Control Mode INTM1 INTM0 Priority Setting Registers Interrupt Mask Bits Description 0 0 0 ICR I Interrupt...

Page 145: ...ipheral Module Interrupt 0 0 O O O All interrupts 1 O X X 1 0 O O O All interrupts 1 0 O X O Interrupts with ICR 1 1 O X X Legend Don t care Note Interrupt control level 1 has priority Default Priorit...

Page 146: ...2 According to the interrupt control level specified in ICR the interrupt controller only accepts an interrupt request with interrupt control level 1 priority and holds pending an interrupt request wi...

Page 147: ...by the contents of the vector address in the vector table Program excution state Interrupt generated NMI An interrupt with interrupt control level 1 IRQ0 IRQ1 MMCIC IRQ0 IRQ1 MMCIC I 0 Save PC and CCR...

Page 148: ...interrupt request is held pending For instance the state transition when the interrupt enable bit corresponding to each interrupt is set to 1 and ICRA to ICRD are set to H 20 H 00 and H 00 respectivel...

Page 149: ...is cleared to 0 An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0 When the I bit is set to 1 only an NMI or address break interrupt request is accepted an...

Page 150: ...interrupt handling routine Yes No Yes Yes Yes No No Yes No Yes No Yes Yes No No Yes Yes No Hold pending I 0 I 0 Yes Yes No No Figure 5 7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt...

Page 151: ...dress bus Internal read signal Internal write signal Internal data bus 3 1 2 4 3 5 7 Instruction prefetch address Instruction is not executed Address is saved as PC contents becoming return address In...

Page 152: ...PC CCR stack save 2 SK 2 SK 4 Vector fetch SI 2 SI 5 Instruction fetch 3 2 SI 2 SI 6 Internal processing 4 2 2 Total using on chip memory 11 to 31 12 to 32 Notes 1 Two states in case of internal inter...

Page 153: ...gnal Interrupt controller I UI SWDTE clear signal Figure 5 9 Interrupt Control for DTC The interrupt controller has three main functions in DTC control Selection of Interrupt Source It is possible to...

Page 154: ...source clearance control according to the settings of the DTCE bit of DTCERA to DTCERE in the DTC and the DISEL bit of MRB in the DTC Table 5 9 Interrupt Source Selection and Clearing Control Setting...

Page 155: ...that interrupt will be executed on completion of the instruction However if there is an interrupt request of higher priority than that interrupt interrupt exception handling will be executed for the...

Page 156: ...7 3 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV B instruction and the EEPMOV W instruction With the EEPMOV B instruction an interrupt request inclu...

Page 157: ...80000 to H FBFFFF can be selected using 18 address pins and the CS256 signal A CP expansion area 8 kbytes basic mode from H FFC000 to H FFDFFF can be selected using 13 address pins and the CPCS1 signa...

Page 158: ...CFA CompactFlashTM Association Bus controller External bus control signals Internal control signals Internal data bus Wait controller BCR2 WSCR2 Bus mode signal Bus arbiter DTC bus acknowledge signal...

Page 159: ...n area is being accessed in mode 2 or when the CPCSE bit in BCR2 is set to 1 CS256 Output Chip select signal indicating that the 256 kbyte expansion area is being accessed in mode 2 or when the CS256E...

Page 160: ...O area range when the AS IOS pin is specified as an I O strobe pin Bit Bit Name Initial Value R W Description 7 1 R W Reserved The initial value should not be changed 6 ICIS 1 R W Idle Cycle Insertio...

Page 161: ...e Select 0 Selects the number of words that can be accessed by burst access via the burst ROM interface 0 Max 4 words 1 Max 8 words 2 CFE 0 R W CF Expansion Area Enable Selects the CP CF expansion are...

Page 162: ...ASTCP bit is cleared to 0 this bit must not be set to 1 6 OWENC 0 R W OE WE Negate Control Specifies the number of delay cycles from CPOE and CPWE signal negation to address hold when the CF expansio...

Page 163: ...he 256 kbyte expansion area and CP CF expansion area For details refer to section 9 I O Ports 2 EXCKS 0 R W External Expansion Clock Select Selects the operating clock used in external expansion area...

Page 164: ...bus width for access to the 256 kbyte expansion area when the CS256E bit in SYSCR is set to 1 0 16 bit bus 1 8 bit bus 6 AST256 1 R W 256 kbyte Expansion Area Access State Control Selects the number o...

Page 165: ...Wait Mode Select 1 0 Select the wait mode for access to the basic expansion area when the AST bit is set to 1 00 Program wait mode 01 Wait disabled mode 10 Pin wait mode 11 Pin auto wait mode When the...

Page 166: ...de 1 Wait disabled mode 6 5 WC11 WC10 1 1 R W R W 256 kbyte Expansion Area Wait Count 1 0 Select the number of program wait states to be inserted for access to the 256 kbyte expansion area when the CS...

Page 167: ...are inserted only for CF expansion area 6 4 Bus Control 6 4 1 Bus Specifications The external address space bus specifications consist of three elements Bus width the number of access states and the...

Page 168: ...t to the CF expansion area memory card mode by the CFE bit in BCR the wait mode and the number of program wait states to be inserted automatically is selected by the WMS21 WMS20 WC22 WC21 and WC20 bit...

Page 169: ...hen RAME 0 used as basic expansion area H FF8000 H FFBFFF 16 kbytes No condition H FFC000 H FFCFFF 4 kbytes CP expansion area 1 CF expansion area When CPCSE 0 used as basic expansion area When CPCSE 1...

Page 170: ...rd Mode H FF F000 H FF F7FF 2 kbytes No condition When IOSE 1 IOS is output and address pins A10 to A0 are used H FF FF00 H FF FF7F 128 bytes When RAME 0 used as basic expansion area Legend This addre...

Page 171: ...Basic expansion area ABW AST WMS1 WMS0 WC1 WC0 ABW256 AST256 WMS10 WC11 WC10 Same as when CS256E 0 0 Used as burst ROM interface 0 ABWCP ASTCP WMS21 WMS20 WC21 WC20 0 1 1 Used as burst ROM interface...

Page 172: ...sic Expansion Area Basic Bus Interface Bus Specifications ABW AST WMS1 WMS0 WC1 WC0 Bus Width Number of Access States Number of Program Wait States 0 16 2 0 0 1 3 0 0 0 0 1 1 0 2 0 1 Other than WMS1 0...

Page 173: ...Bus Specifications for 256 kbyte Expansion Area Basic Bus Interface Bus Specifications ABW256 AST256 WMS10 WC11 WC10 Bus Width Number of Access States Number of Program Wait States 0 16 2 0 1 3 0 0 0...

Page 174: ...Area Basic Mode Basic Bus Interface Bus Specifications ABWCP ASTCP WMS21 WMS20 WC21 WC20 Bus Width Number of Access States Number of Program Wait States 0 16 2 0 0 1 3 0 0 0 0 1 1 0 2 0 1 Other than...

Page 175: ...FFF000 to H FFF7FF can be accessed by specifying the AS IOS pin as an I O strobe pin The 256 kbyte expansion area H F80000 to H FBFFFF and CP expansion area H FFC000 to H FFDFFF can be accessed by th...

Page 176: ...low when the corresponding external address space is accessed Figure 6 2 shows an example of IOS signal output timing Bus cycle T1 T2 Address bus IOS T3 External addresses selected by IOS Figure 6 2 I...

Page 177: ...r the 8 bit access space With the 8 bit access space the upper data bus D15 to D8 is always used for accesses The amount of data that can be accessed at one time is one byte a word access is performed...

Page 178: ...WR signal is valid for the upper half of the data bus and the LWR signal for the lower half Table 6 9 Data Buses Used and Valid Strobes Area Access Size Read Write Address Valid Strobe Upper Data Bus...

Page 179: ...o D8 of the data bus is used Wait states cannot be inserted Bus cycle T1 T2 Address bus AS IOS IOSE 1 CS256 CS256E 1 CPCS1 CPCSE 1 and CFE 0 AS IOS IOSE 0 RD D15 to D8 Valid D7 to D0 Invalid Read HWR...

Page 180: ...ta bus is used Wait states can be inserted Bus cycle T1 T2 Address bus AS IOS IOSE 0 RD D15 to D8 Valid D7 to D0 Invalid Read HWR D15 to D8 Valid Write T3 AS IOS IOSE 1 CS256 CS256E 1 CPCS1 CPCSE 1 an...

Page 181: ...to D0 for odd addresses Wait states cannot be inserted Bus cycle T1 T2 Address bus AS IOS IOSE 0 RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 Undefined Write High level AS...

Page 182: ...LWR D15 to D8 Undefined D7 to D0 Valid Write High level AS IOS IOSE 1 CS256 CS256E 1 CPCS1 CPCSE 1 and CFE 0 Note For external address space access this signal is not output when the 256 kbyte expans...

Page 183: ...Read HWR LWR D15 to D8 Valid D7 to D0 Valid Write AS IOS IOSE 1 CS256 CS256E 1 CPCS1 CPCSE 1 and CFE 0 Note For external address space access this signal is not output when the 256 kbyte expansion ar...

Page 184: ...to D0 for odd addresses Wait states can be inserted Bus cycle T1 T2 Address bus AS IOS IOSE 0 RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 Undefined Write High level T3 AS...

Page 185: ...WR D15 to D8 Undefined D7 to D0 Valid Write High level T3 AS IOS IOSE 1 CS256 CS256E 1 CPCS1 CPCSE 1 and CFE 0 Note For external address space access this signal is not output when the 256 kbyte expan...

Page 186: ...ead HWR LWR D15 to D8 Valid D7 to D0 Valid Write T3 AS IOS IOSE 1 CS256 CS256E 1 CPCS1 CPCSE 1 and CFE 0 Note For external address space access this signal is not output when the 256 kbyte expansion a...

Page 187: ...the WC1 and WC0 bits the WC21 and WC20 bits for the CP expansion area If the WAIT CPWAIT pin is low at the falling edge of in the last T2 or TW state another TW state is inserted If the WAIT CPWAIT pi...

Page 188: ...yte expansion area is accessed with CS256E 1 and when the CP CF expansion area is accessed with CPCSE 1 WAIT CPWAIT Data bus T2 TW TW TW T3 By WAIT CPWAIT pin Figure 6 13 Example of Wait State Inserti...

Page 189: ...ing of the BRSTS1 bit in BCR Wait states cannot be inserted in a burst cycle Burst accesses of a maximum four words is performed when the BRSTS0 bit in BCR is cleared to 0 and burst accesses of a maxi...

Page 190: ...ead data Read data AS IOS IOSE 0 Figure 6 15 Access Timing Example in Burst ROM Space AST BRSTS1 0 6 6 2 Wait Control As with the basic bus interface program wait insertion or pin wait insertion using...

Page 191: ...Data Size and Data Alignment The data sizes for the CPU and other internal bus masters are byte word and longword The BSC has a data alignment function and controls whether the upper data bus D15 to...

Page 192: ...Write L L CPWE Valid odd data Valid even data Notes Undefined Undefined data is output Invalid Input state with the input value ignored 6 7 3 Basic Operation Timing The memory card interface is basic...

Page 193: ...PCS2 CPOE CPWE D15 to D0 D15 to D0 Valid Read Valid Write T3 Figure 6 17 Access Timing in Memory Card Mode Basic Cycle By program wait T1 T2 TW TW Address bus CPCS1 CPCS2 CPOE CPWE D15 to D0 D15 to D0...

Page 194: ...T2 state and T3 state when accessing the CF expansion area according to the settings in the WC22 WC21 and WC20 bits If the CPWAIT pin is low at the falling edge of in the last T2 or TW state another...

Page 195: ...an idle cycle is inserted at the start of the write cycle Figure 6 20 shows examples of idle cycle operation In these examples bus cycle A is a read cycle for ROM with a long output floating time and...

Page 196: ...ite operations when they have possession of the bus 6 9 1 Bus Master Priority Each bus master requests the bus by means of a bus request signal The bus arbiter detects the bus masters bus request sign...

Page 197: ...ansferred at a break between bus cycles Even in discrete operations as in the case of a longword size access the bus can be transferred between the component operations For details refer to section 8...

Page 198: ...Section 6 Bus Controller Rev 3 00 Jan 25 2006 page 144 of 872 REJ09B0286 0300...

Page 199: ...n chip RAM 1 kbyte enabling 32 bit 1 state reading and writing of the DTC register information 7 1 Features Transfer is possible over any number of channels Three transfer modes Normal repeat and bloc...

Page 200: ...DTC activation request Control logic Register information Figure 7 1 Block Diagram of DTC 7 2 Register Descriptions The DTC has the following registers DTC mode register A MRA DTC mode register B MRB...

Page 201: ...2 when Sz 1 5 4 DM1 DM0 Undefined Undefined Destination Address Mode 1 0 These bits specify a DAR operation after a data transfer 0X DAR is fixed 10 DAR is incremented after a transfer by 1 when Sz 0...

Page 202: ...ansfer In data transfer with CHNE set to 1 determination of the end of the specified number of data transfers clearing of the interrupt source flag and clearing of DTCER are not performed 6 DISEL Unde...

Page 203: ...ormal mode the entire CRA functions as a 16 bit transfer counter 1 to 65536 It is decremented by 1 every time data is transferred and transfer ends when the count reaches H 0000 In repeat mode or bloc...

Page 204: ...R W R W DTC Activation Enable Setting this bit to 1 specifies a relevant interrupt source as a DTC activation source Clearing conditions When data transfer has ended with the DISEL bit in MRB set to 1...

Page 205: ...ansfers have not ended 2 When 0 is written to the DISEL bit after a software activated data transfer end interrupt SWDTEND request has been sent to the CPU This bit will not be cleared when the DISEL...

Page 206: ...0 for example is the RDRF flag in SCI_0 When an interrupt has been designated as a DTC activation source the existing CPU mask level and interrupt controller priorities have no effect If there is more...

Page 207: ...be located at the vector address corresponding to the interrupt source in the DTC vector table The DTC reads the start address of the register information from the vector table set for each activation...

Page 208: ...TMR_X CMIAX 44 H 0458 DTCEC3 CMIBX 45 H 045A DTCED0 FRT ICIA 48 H 0460 DTCEA2 ICIB 49 H 0462 DTCEA1 OCIA 52 H 0468 DTCEA0 OCIB 53 H 046A DTCEB7 TMR_0 CMIA0 64 H 0480 DTCEB2 CMIB0 65 H 0482 DTCEB1 TMR_...

Page 209: ...DTCED3 IICT1 99 H 04C6 DTCED2 Reserved for system use 104 H 04D0 DTCEE3 Reserved for system use 105 H 04D2 DTCEE2 Reserved for system use 106 H 04D4 DTCEE1 Reserved for system use 107 H 04D6 DTCEE0 U...

Page 210: ...fied as normal repeat or block transfer mode Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation source chain transfer The 24 bit SAR designate...

Page 211: ...nsfers can be specified Once the specified number of transfers have been completed a CPU interrupt can be requested Table 7 3 Register Functions in Normal Mode Name Abbreviation Function DTC source ad...

Page 212: ...at area is restored and transfer is repeated In repeat mode the transfer counter value does not reach H 00 and therefore CPU interrupts cannot be requested when the DISEL bit in MRB is cleared to 0 Ta...

Page 213: ...estored The other address register is then incremented decremented or left fixed according to the register information From 1 to 65 536 transfers can be specified Once the specified number of transfer...

Page 214: ...ster information at that start address After the data transfer the CHNE bit will be tested When it has been set to 1 DTC reads the next register information located in a consecutive area and performs...

Page 215: ...activated data transfer end interrupt SWDTEND is generated When the DISEL bit is 1 and one data transfer has been completed or the specified number of transfers have been completed after data transfer...

Page 216: ...Transfer information write Data transfer Figure 7 10 DTC Operation Timing Example of Block Transfer Mode with Block Size of 2 DTC activation request DTC request Address Vector read Read Write Read Wri...

Page 217: ...External Devices Bus width 32 16 16 8 16 8 8 16 16 Access states 1 1 1 2 2 2 3 2 3 Vector read SI 1 4 6 2m 2 3 m Execution status Register information read write SJ 1 Byte data read SK 1 1 1 2 2 2 3 m...

Page 218: ...ure for using the DTC with software activation is as follows 1 Set the MRA MRB SAR DAR CRA and CRB register information in on chip RAM 2 Set the start address of the register information in the DTC ve...

Page 219: ...ample is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation The transfer source address is H 1000 and the transfer destination address is H 2000 Th...

Page 220: ...riting Multiple DTC activation sources can be set at one time only at the initial setting by masking all interrupts and writing data after executing a dummy read on the relevant register 7 8 4 Setting...

Page 221: ...ta transfer A block diagram of the RFU is shown in figure 8 1 8 1 Features Bus master with priority higher than that of the CPU and DTC Provides the RFU ID to specific peripheral modules SCI USB and M...

Page 222: ...signal Legend BAR Base address register RAR Read address pointer TMP Temporary pointer WAR Write address pointer DATAN Valid data byte number FREEN Free area byte number NRA Read start address NWA Wri...

Page 223: ...ta transfer status register A DTSTRA Data transfer status register B DTSTRB Data transfer control register C DTCRC Data transfer control register D DTCRD Data transfer interrupt enable register DTIER...

Page 224: ...These bits specify a RAM base address that can be used as the FIFO 3 to 0 All 0 R Base Addresses 3 to 0 These bits are always read as 0 and cannot be modified 8 2 3 Read Address Pointer RAR RAR is an...

Page 225: ...h RAM write cycle However these bits are not incremented and cleared to 0 when exceeding the selected FIFO size 8 2 5 Temporary Pointer TMP TMP is an 11 bit pointer provided in each pointer set and al...

Page 226: ...by FIFO in each pointer set 8 2 7 Free Area Byte Number FREEN FREEN is 11 bit status data allocated to bits 10 to 0 in FSTR Bit Bit Name Initial Value R W Description 31 to 11 All 0 R Reserved These b...

Page 227: ...rols the operation of each pointer set Bit Bit Name Initial Value R W Description 7 IDE A 0 R W ID A Enable Enables disables ID A selected by DTIDR 0 Disables ID A 1 Enables ID A 6 IDE B 0 R W ID B En...

Page 228: ...to BUD0 bits Since the lower bits become invalid 0 should be written to these bits In RAR WAR and TMP the bits lower than the boundary become valid Since the upper bits become invalid 0 should be wri...

Page 229: ...r to reflect WAR boundary overflow to the BOVF_W flag in DTSTRC 0 Boundary overflow at writing is not reflected to the BOVF_W flag 1 Boundary overflow at writing is reflected to the BOVF_W flag 5 FULL...

Page 230: ...ry pointer is used the contents of RAR are copied to TMP When the write temporary pointer is used the contents of WAR are copied to TMP 1 REST 0 W Pointer Reset When this bit is set to 1 this bit init...

Page 231: ...n of WAR RAR or TMP WAR when the read temporary pointer is selected according to the write bus cycle This flag can be masked by the FULLE bit in DTCRB 4 EMPTY 0 R W FIFO Empty Indicates detection of F...

Page 232: ...R W Description 7 6 5 4 ID A3 ID A2 ID A1 ID A0 0 0 0 0 R W R W R W R W ID A Select These bits write the ID number to be selected by the IDE A bit 3 2 1 0 ID B3 ID B2 ID B1 ID B0 0 0 0 0 R W R W R W...

Page 233: ...R W R W R W R W R W ID7 R W to ID0 R W These bits select the direction for transferring peripheral modules with ID numbers 7 to 0 0 RAM Peripheral modules write 1 Peripheral modules read RAM 8 2 16 D...

Page 234: ...rrupt flags for pointer set numbers 3 to 1 0 No interrupt source 1 Either flag of OVER_R or OVER_W is set to 1 0 DTEIE 0 R W Data Transfer Error Interrupt Enable 0 Disables an interrupt generated by D...

Page 235: ...ointer set 1 Enables pointer set 8 2 20 Data Transfer Interrupt Enable Register DTIER Bit Bit Name Initial Value R W Description 7 to 4 All 0 R W Reserved The initial value should not be changed 3 2 1...

Page 236: ...lect the register pointer to be accessed by FSTR while the RS bit is 0 00 The base address register BAR is accessed by FSTR 01 The read address pointer RAR is accessed by FSTR 10 The write address poi...

Page 237: ...ity The ID is classified into two groups and the priority inter groups is fixed The initial priority in the group is as shown in table 8 2 However the priority is changed whenever the RFU performs pro...

Page 238: ...s to clear the request All RFU bus cycles are executed in two states In the RFU bus cycle data transfer is executed or the error status is notified in addition to clearing a request and the RFU pointe...

Page 239: ...he handshake is approved the contents of RAR WAR are regarded as the formal contents of the pointer and are sent to TMP mark operation When the handshake is refused the contents of RAR WAR are restore...

Page 240: ...R addition RAM read peripheral module write cycle Notification of FIFO empty state Adds RAR RAM peripheral modules TMP is used as a read temporary pointer RAR WAR Notification of FIFO overread state N...

Page 241: ...ly No pointer manipulations TMP is used as a read temporary pointer Acknowledge only RAR TMP Pointer mark TMP is used as a write temporary pointer Acknowledge only WAR TMP TMP is not used Acknowledge...

Page 242: ...de The clock division in the medium speed mode should be temporarily suspended to switch the clock to high speed mode by setting the DTSPEED bit in SBYCR to 1 during DTC and RFU operations and during...

Page 243: ...bled Disabled The end of each CPU bus cycle for bit manipulation instruction Enabled Disabled The end of CPU bus cycle for CCR manipulation instruction Enabled Disabled The end of each CPU bus cycle f...

Page 244: ...tes for external extension To reduce the RFU response time it is recommended to set the external extension area access to 3 states no waits SB0V 1 SB1V 2 T1 T1 T1 T1 T1 T1 T2 T2 T2 T2 T2 T2 CPU bus cy...

Page 245: ...start address of the pointer status and the number of valid data bytes are used When the CPU generates data to be transmitted data is written to on chip RAM and then the RAM address where data is stor...

Page 246: ...occurs At this time the BOVF_W flag in DTSTRC is set to 1 8 8 2 Transmission Reception of Consecutive Data Blocks If the peripheral module includes a function to generate an interrupt request at the c...

Page 247: ...buffer and operates such that the transmit buffer is always filled When the transmission for MAX_PACKET_SIZE bytes is completed the USB issues a mark reload rewind request to the RFU according to the...

Page 248: ...hip RAM 10 kbytes Data area for communication pipe 1 32 to 2048 bytes Data area for communication pipe 2 32 to 2048 bytes EP4 transmit buffer 2 byte buffer EP5 receive buffer 2 byte buffer Data mark r...

Page 249: ...Yes Yes Yes Set the EP4TS interrupt flag Request USBID interrupt IDLE Manipulate pointer update to the RFU Transmit STALL packet Transmit NAK packet End data transmission abnormally Set the EP4TF inte...

Page 250: ...rrupt IDLE Manipulate pointer update to the RFU Transmit STALL packet Transmit NAK packet End data transmission abnormally Set the EP5TF interrupt flag Manipulate pointer rewind to the RFU No handshak...

Page 251: ...he RDRF flag Figure 8 8 shows the operational flow for transmission When the transmitted data is written to the FIFO and start of transmission is triggered the TDRE and RDRF flags in SSR are set to 1...

Page 252: ...alize the RFU Start transmission Overread RAM data TEND 1 End No TDRE 1 No No Yes Yes Yes Transfer transmit data from RAM to TDR Set TDRE_DTE in SCIDTER to 1 Set TE in SCR to 1 Initialize the SCI RFU...

Page 253: ...ize the RFU RFU activation request Set RDRF_DTE in SCIDTER to 1 Set RE in SCR to 1 Start reception RDRF_DTE in SCIDTER are automatically cleared to 0 End RDRF 1 No No Yes Yes Initialize the SCI Transf...

Page 254: ...ten to the RFU and start of transmission is triggered the DATAEN bit in OPCR is set the MCIF issues a data transfer request to the RFU Figure 8 12 shows the operational flow for reception Multimedia c...

Page 255: ...NO YES YES YES YES YES YES Hardware MCIF RFU Firmware CPU Command transmission data transmission to multimedia card Command transmission data transmission to multimedia card Data transmission end Dat...

Page 256: ...ption ended FIFO full FIFO full Data reception command sequence ended Command sequence end Data read from RFU ended FIFO full cancellation data read from RFU Figure 8 12 Operation Flow of MCIF Recepti...

Page 257: ...and pointer mode Set DTCRA Sz BUD 2 0 PMD1 PMD0 Set DTCRB Set DTIDR DTIDSRA DTIDSRSB Set DTIER Set DTCRA IDE A IDE B Set the base address Assign an ID and set the transfer direction Set DTE bit in DTC...

Page 258: ...or FIFO empty state when the conditions listed in table 8 7 are satisfied the read values may not be correct When DATAN or FREEN is read as 0 whether the FIFO is full or empty needs to be checked by...

Page 259: ...n drive a single TTL load and 30 pF capacitive load All the I O ports can drive a Darlington transistor when in output mode Port 8 is an NMOS push pull output Table 9 1 Port Functions Extended Mode Si...

Page 260: ...MCIF input output D8 CPD8 P30 WUE8 MCCLK Built in input pull up MOSs LED drive capability sink current 5 mA Port 4 General I O port also functioning as interrupt input TMR_0 TMR_1 TMR_X TMR_Y timer co...

Page 261: ...S P62 FTIA CIN2 KIN2 VSYNCI 1 D2 CPD2 2 P62 FTIA CIN2 KIN2 VSYNCI TXENL P61 FTOA CIN1 KIN1 VSYNCO 1 D1 CPD1 2 P61 FTOA CIN1 KIN1 VSYNCO SUSPEND Port 6 General I O port also functioning as bidirectiona...

Page 262: ...0 SCL1 P81 ExIRQ9 SDA0 P80 ExIRQ8 SCL0 P87 to P80 are NMOS push pull outputs SDA1 SCL1 SDA0 and SCL0 are NMOS open drain outputs P97 WAIT CPWAIT CS256 P97 P96 EXCL AS IOS P95 HWR CPWE P94 RD CPOE P93...

Page 263: ...ister P1PCR 9 1 1 Port 1 Data Direction Register P1DDR The individual bits of P1DDR specify input or output for the pins of port 1 Bit Bit Name Initial Value R W Description 7 P17DDR 0 W 6 P16DDR 0 W...

Page 264: ...ral output port If a port 1 read is performed while the P1DDR bits are set to 1 the P1DR values are read If a port 1 read is performed while the P1DDR bits are cleared to 0 the pin states are read 9 1...

Page 265: ...nction of port 1 pins is switched as shown below according to the combination of the OEn bit in PWOERA of PWM and the P1nDDR bit P1nDDR 0 1 OEn 0 1 Pin function P17 to P10 input pins P17 to P10 output...

Page 266: ...DDR The individual bits of P2DDR specify input or output for the pins of port 2 Bit Bit Name Initial Value R W Description 7 P27DDR 0 W 6 P26DDR 0 W 5 P25DDR 0 W 4 P24DDR 0 W 3 P23DDR 0 W 2 P22DDR 0 W...

Page 267: ...ral output port If a port 2 read is performed while the P2DDR bits are set to 1 the P2DR values are read If a port 2 read is performed while the P2DDR bits are cleared to 0 the pin states are read 9 2...

Page 268: ...and 11 in the following table are expressed by the following logical expressions Address 13 1 ADFULLE CS256E IOSE Address 11 1 ADFULLE CS256E CPCSE IOSE P2nDDR 0 1 Address 13 0 1 Pin function P27 to P...

Page 269: ...MOS can be used regardless of the operating mode Table 9 3 summarizes the input pull up MOS states Table 9 3 Port 2 Input Pull Up MOS States Reset Hardware Standby Mode Software Standby Mode In Other...

Page 270: ...are set to 1 and input ports when cleared to 0 9 3 2 Port 3 Data Register P3DR P3DR stores output data for the port 3 pins Bit Bit Name Initial Value R W Description 7 P37DR 0 R W 6 P36DR 0 R W 5 P35D...

Page 271: ...ed on when a P3PCR bit is set to 1 9 3 4 Pin Functions The relationship between register setting values and pin functions are as follows in each operating mode Note that MMC mode stands for MultiMedia...

Page 272: ...in To use this pin as the WUE14 input pin clear the P36DDR bit to 0 P36DDR 0 1 P36 input pin P36 output pin Pin function WUE14 input pin P35 WUE13 The pin function is switched as shown below according...

Page 273: ...se this pin as the WUE12 input pin clear the P34DDR bit to 0 MCIF disable MMCPE in IOMCR is 0 or MMCS in PTCNT0 is 1 MCIF enable MMCPE in IOMCR is 1 MMCS in PTCNT0 is 0 MCIF operating mode MCIF enable...

Page 274: ...ME in IOMCR is 0 MMC mode SPI in MODER is 0 DIRME in IOMCR is 1 SPI mode SPI in MODER is 1 P33DDR 0 1 P33 input pin P33 output pin MCDATDIR output pin MCCSA output pin Pin function WUE11 input pin P32...

Page 275: ...in PTCNT0 is 1 MMC mode SPI in MODER is 0 SPI mode SPI in MODER is 1 P31DDR 0 1 P31 input pin P31 output pin MCCMD input output pin MCTxD output pin Pin function WUE9 input pin P30 WUE8 MCCLK The pin...

Page 276: ...ode Reset Hardware Standby Mode Software Standby Mode In Other Operations Extended mode EXPE 1 Off Off Off Off Single chip mode EXPE 0 Off Off On Off On Off Legend Off Always off On Off On when input...

Page 277: ...orresponding port 4 pins are output ports when the P4DDR bits are set to 1 and input ports when cleared to 0 9 4 2 Port 4 Data Register P4DR P4DR stores output data for the port 4 pins Bit Bit Name In...

Page 278: ...as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_X and the P46DDR bit When the ISS6 bit in ISSR is cleared to 0 and the IRQ6E bit in IER of the interrupt controller i...

Page 279: ...ble MMCPE in IOMCR is 0 or Single chip mode EXPE 0 MMCS in PTCNT0 is 0 MCIF enable MMCPE in IOMCR is 1 MMCS in PTCNT0 is 1 or Extended mode EXPE 1 MCIF operating mode MCIF enable MMCPE in IOMCR is 1 M...

Page 280: ...nput pin P42 IRQ2 TMO0 ExMCDAT ExMCRxD The pin function is switched as shown below according to the combination of the MCIF operating mode the OS3 to OS0 bits in TCSR of TMR_1 and the P42DDR bit When...

Page 281: ...NCI input pin MCIF enable MMCPE in IOMCR is 1 MMCS in PTCNT0 is 1 or Extended mode EXPE 1 MCIF operating mode MCIF disable MMCPE in IOMCR is 0 or Single chip mode EXPE 0 MMCS in PTCNT0 is 0 MMC mode S...

Page 282: ...on as interrupt input pins the PWMX output pin SCI_0 SCI_1 and SCI_2 input output pins Port 5 has the following registers Port 5 data direction register P5DDR Port 5 data register P5DR 9 5 1 Port 5 Da...

Page 283: ...rt 5 read is performed while the P5DDR bits are cleared to 0 the pin states are read 9 5 3 Pin Functions The relationship between register setting values and pin functions are as follows In the tables...

Page 284: ...of the RE bit in SCR of SCI_2 and the P55DDR bit When the IRQ13E bit in IER16 of the interrupt controller is set to 1 or the ISS13 bit in ISSR16 is cleared to 0 this pin can be used as the IRQ13 inpu...

Page 285: ...bination of the TE bit in SCR of SCI_1 and the P52DDR bit When the IRQ10E bit in IER16 of the interrupt controller is set to 1 or the ISS10 bit in ISSR16 is cleared to 0 this pin can be used as the IR...

Page 286: ...to 0 TE 0 1 P50DDR 0 1 P50 input pin P50 output pin TxD0 output pin Pin function IRQ8 input pin 9 6 Port 6 Port 6 is an 8 bit I O port Port 6 pins also function as the FRT input output pin enhanced A...

Page 287: ...the P6DDR bits are set to 1 and input ports when cleared to 0 9 6 2 Port 6 Data Register P6DR P6DR stores output data for the port 6 pins Bit Bit Name Initial Value R W Description 7 P67DR 0 R W 6 P66...

Page 288: ...Bit Bit Name Initial Value R W Description 7 KM7PCR 0 R W 6 KM6PCR 0 R W 5 KM5PCR 0 R W 4 KM4PCR 0 R W 3 KM3PCR 0 R W 2 KM2PCR 0 R W 1 KM1PCR 0 R W 0 KM0PCR 0 R W Extended mode 16 bit data bus Operati...

Page 289: ...selected 10 Input level 2 is selected 11 Input level 3 is selected 5 P6PUE 0 R W Port 6 Input Pull Up Extra Selects the current specification for the input pull up MOS connected by means of KMPCR set...

Page 290: ...nput output pins or I O port In single chip mode port 6 pins function as the FRT input output pin enhanced A D conversion input pin keyboard input pin timer connection input output pins or external US...

Page 291: ...KBCOMP of the A D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B 101 this pin can be used as the CIN5 input pin When the KMIM5 bit in KMIMR6 of the interrupt controller is cleared t...

Page 292: ...the timer connection are cleared to B 00 this pin can be used as the VFBACKI input pin P63DDR 0 1 P63 input pin P63 output pin Pin function FTIB input pin CIN3 input pin KIN3 input pin VFBACKI input...

Page 293: ...ut pin VSYNCO output pin Pin function CIN1 input pin KIN1 input pin P60 FTCI CIN0 KIN0 HFBACKI The function of port 6 pins is switched as shown below according to the P60DDR bit When the CKS1 and CKS0...

Page 294: ...pin P67 output pin DPLS input pin Pin function CIN7 input pin KIN7 input pin P66 FTOB CIN6 KIN6 CBLANK DMNS The function of port 6 pins is switched as shown below according to the combination of the F...

Page 295: ...n be used as the CSYNCI input pin FADSEL 0 1 P65DDR 0 1 P65 input pin P65 output pin XVERDATA input pin Pin function FTID input pin CIN5 input pin KIN5 input pin CSYNCI input pin P64 FTIC CIN4 KIN4 CL...

Page 296: ...EL 0 1 P63DDR 0 1 P63 input pin P63 output pin TXDMNS output pin Pin function FTIB input pin CIN3 input pin KIN3 input pin VFBACKI input pin P62 FTIA CIN2 KIN2 VSYNCI TXENL The function of port 6 pins...

Page 297: ...END output pin Pin function CIN1 input pin KIN1 input pin P60 FTCI CIN0 KIN0 HFBACKI SPEED The function of port 6 pins is switched as shown below according to the combination of the FADSEL bit in USBC...

Page 298: ...rt 7 pins also function as the A D converter analog input pins D A converter analog output pins and interrupt input pins When the ISS bit in ISSR is set to 1 these pins can be used as the interrupt in...

Page 299: ...t 8 is an NMOS push pull output Port 8 has the following registers Port 8 data direction register P8DDR Port 8 data register P8DR 9 8 1 Port 8 Data Direction Register P8DDR The individual bits of P8DD...

Page 300: ...In the tables the symbol stands for Don t care P87 ExIRQ15 ADTRG ExTMIY USEXCL The pin function is switched as shown below according to the P87DDR bit When the TRGS1 and TRGS0 bits in ADCR of the A D...

Page 301: ...1 P86DDR 0 1 P86 input pin P86 output pin SCK2 output pin SCK2 output pin SCK2 input pin Pin function ExIRQ14 input pin ExTMIX input pin P85 ExIRQ13 SCK1 ExTMI1 The pin function is switched as shown b...

Page 302: ...w according to the combination of the ICE bit in ICCR of IIC_1 and the P83DDR bit When the ISS11 bit in ISSR16 of the interrupt controller is set to 1 this pin can be used as the ExIRQ11 input pin To...

Page 303: ...The output format for SDA0 is NMOS open drain output and direct bus drive is possible ICE 0 1 P81DDR 0 1 P81 input pin P81 output pin SDA0 input output pin Pin function ExIRQ9 input pin P80 ExIRQ8 SC...

Page 304: ...ster P9DDR The individual bits of P9DDR specify input or output for the pins of port 9 Bit Bit Name Initial Value R W Description 7 P97DDR 0 W If port 9 pins are specified for use as the general I O p...

Page 305: ...its are cleared to 0 the pin states are read Note The initial value of bit 6 is determined according to the P96 pin state 9 9 3 Pin Functions The relationship between the operating mode register setti...

Page 306: ...perating Mode Extended Mode Single Chip Mode P95DDR 0 1 IOSE 0 1 Pin function AS output pin IOS output pin P95 input pin P95 output pin P94 HWR CPWE The pin function is switched as shown below accordi...

Page 307: ...ination of the operating mode the CPCSE bit in BCR2 of BSC the CFE bit in BCR and the P91DDR bit Operating Mode Extended Mode Single Chip Mode CPCSE and CFE Either bit is 0 Both bits are 1 P91DDR 0 1...

Page 308: ...All 0 W Reserved These bits cannot be modified 1 PA1DDR 0 W 0 PA0DDR 0 W In extended mode mode 2 The corresponding port A pins are address output ports when the PADDR bits are set to 1 and input ports...

Page 309: ...n t care Extended Mode Mode 2 PA1 A17 KIN9 SSE2I The function of port A pins is switched as shown below according to the combination of the SSE bit in SEMR of SCI_2 the C A bit in SMR the CKE1 bit in...

Page 310: ...n as the KIN8 input pin clear the PA0DDR bit to 0 SSE 0 1 C A 1 CKE1 1 PA0DDR 0 1 1 Address 13 1 0 PA0 input pin PA0 output pin A16 output pin SSE0I Pin function KIN8 input pin Note Even if SSE 0 PA0D...

Page 311: ...N8 input pin 9 10 5 Input Pull Up MOS Port A has a built in input pull up MOS that can be controlled by software This input pull up MOS can be used in any operating mode and can be specified as on or...

Page 312: ...peripheral function description the original pin name is used 9 11 1 IRQ Sense Port Select Register 16 ISSR16 IRQ Sense Port Select Register ISSR ISSR16 and ISSR select ports that also function as IRQ...

Page 313: ...ISS6 0 R W 0 P46 IRQ6 is selected 1 P76 ExIRQ6 is selected 5 ISS5 0 R W 0 P45 IRQ5 is selected 1 P75 ExIRQ5 is selected 4 ISS4 0 R W 0 P44 IRQ4 is selected 1 P74 ExIRQ4 is selected 3 ISS3 0 R W 0 P43...

Page 314: ...d 1 P85 ExTMI1 is selected 5 TMIXS 0 R W 0 P44 TMIX is selected 1 P86 ExTMIX is selected 4 TMIYS 0 R W 0 P45 TMIY is selected 1 P87 ExTMIY is selected 3 MMCS 0 R W 0 P30 MCCLK P31 MCCMD MCTxD P32 MCDA...

Page 315: ...veforms are generated from a common time base enabling PWM output with a high carrier frequency to be produced using pulse division 10 1 Features Operable at a maximum carrier frequency of 1 25 MHz us...

Page 316: ...DR0 PWDR1 PWDR2 PWDR3 PWDR4 PWDR5 PWDR6 PWDR7 PWDR8 PWDR9 PWDR10 PWDR11 PWDR12 PWDR13 PWDR14 PWDR15 PWSL 8 PWDPRB PWOERB P2DDR P2DR PWDPRA PWOERA P1DDR P1DR Legend PWSL PWDR PWDPRA PWDPRB PWOERA PWOER...

Page 317: ...iptions The PWM has the following registers To access PCSR the FLSHE bit in the serial timer control register STCR must be cleared to 0 For details on the serial timer control register STCR see sectio...

Page 318: ...TCNT in the PWM For details see table 10 2 The resolution PWM conversion period and carrier frequency depend on the selected internal clock and can be obtained from the following equations Resolution...

Page 319: ...d 0011 PWDR3 selected 0100 PWDR4 selected 0101 PWDR5 selected 0110 PWDR6 selected 0111 PWDR7 selected 1000 PWDR8 selected 1001 PWDR9 selected 1010 PWDR10 selected 1011 PWDR11 selected 1100 PWDR12 sele...

Page 320: ...d The upper four bits specify the duty cycle of the basic pulse as 0 16 to 15 16 with a resolution of 1 16 The lower four bits specify how many extra pulses are to be added within the conversion perio...

Page 321: ...dth of output 1 PWM inverted output PWDR value corresponds to low width of output 10 3 4 PWM Output Enable Registers A and B PWOERA and PWOERB Each PWOER switches between PWM output and port output PW...

Page 322: ...10 Port output or PWM 256 256 output 11 PWM output 0 to 255 256 output Legend X Don t care To perform PWM 256 256 output when DDR 1 and OE 0 the corresponding pin should be set to port output The corr...

Page 323: ...initial value should not be changed 5 4 PWCKXB PWCKXA 0 0 R W R W See section 11 3 4 Peripheral Clock Select Register PCSR 3 0 R Reserved This bit is always read as 0 and cannot be modified 2 1 PWCKB...

Page 324: ...ycle of the basic pulse as 0 16 to 15 16 with a resolution of 1 16 Table 10 4 shows the duty cycles of the basic pulse Table 10 4 Duty Cycle of Basic Pulse 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Upper 4 Bi...

Page 325: ...Pulses Basic Pulse No Lower 4 Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 B 0000 B 0001 Yes B 0010 Yes Yes B 0011 Yes Yes Yes B 0100 Yes Yes Yes Yes B 0101 Yes Yes Yes Yes Yes B 0110 Yes Yes Yes Yes Y...

Page 326: ...Section 10 8 Bit PWM Timer PWM Rev 3 00 Jan 25 2006 page 272 of 872 REJ09B0286 0300...

Page 327: ...ual to T 64 or T 256 where T is the resolution Eight operating speeds Eight operation clocks by combination of four resolution settings and two base cycle settings Figure 11 1 shows a block diagram of...

Page 328: ...ssigned to the same addresses with other registers The registers are selected by the IICE bit in the serial timer control register STCR To access PCSR the FLSHE bit in STCR must be cleared to 0 For de...

Page 329: ...8 bit units DACNT should always be accessed in 16 bit units For details see section 11 4 Bus Master Interface DACNTH DACNTL 15 14 13 12 11 10 9 8 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 Bit CPU Bit counter...

Page 330: ...a digital value to be converted to an analog value In each base cycle the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform and to decide wheth...

Page 331: ...range that depends on the CFS bit If the DADR value is outside this range the PWM output is held constant A channel can be operated with 12 bit precision by keeping both the DA0 and DA1 bits cleared...

Page 332: ...el B output at the PWX1 pin is disabled 1 PWM D A channel B output at the PWX1 pin is enabled 2 OEA 0 R W Output Enable A Enables or disables output on PWM D A channel A 0 PWM D A channel A output at...

Page 333: ...R W R W PWMX Clock Select Select the clock when the CKS bit in DACR of PWMX is set to 1 00 Operates at resolution T system clock cycle time tcyc 2 01 Operates at resolution T system clock cycle time...

Page 334: ...d the lower byte value is transferred to TEMP Next when the lower byte is read from the lower byte value in TEMP is transferred to the CPU These registers should always be accessed 16 bits at a time w...

Page 335: ...put When OS 1 the output waveform is inverted and the DADR value corresponds to the total width TH of the high 1 output pulses Figures 11 3 and 11 4 show the types of waveform output available tf tL T...

Page 336: ...2 Data value T DADR H 0401 to H FFFD 10 0 0 0 0 81 92 14 1310 72 12 0 0 327 68 0 0 1 0 08 1 20 48 48 8 kHz 1310 72 763 Hz 1 Always low high output DADR H 0003 to H 00FF 2 Data value T DADR H 0103 to...

Page 337: ...5 tL256 1 conversion cycle tf1 tf2 tf3 tf255 tf256 T 64 tL1 tL2 tL3 tL255 tL256 TL tf1 tf2 tf63 tf64 tL1 tL2 tL3 tL63 tL64 1 conversion cycle tf1 tf2 tf3 tf63 tf64 T 256 tL1 tL2 tL3 tL63 tL64 TL a CFS...

Page 338: ...t Waveform OS 1 DADR corresponds to TH An example of the additional pulses when CFS 1 base cycle resolution T 256 and OS 1 inverted PWMX output is described below When CFS 1 the upper eight bits DA13...

Page 339: ...ut only at the location of base pulse No 63 according to table 11 4 Thus an additional pulse of 1 256 T is to be added to the base pulse 1 conversion cycle Base pulse High width 2 256 T Base pulse 2 2...

Page 340: ...0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1...

Page 341: ...orms can be output Four independent input capture channels The rising or falling edge can be selected Buffer modes can be specified Counter clearing The free running counters can be cleared on compare...

Page 342: ...IC ICID Interrupt signal Legend OCRA OCRB OCRAR OCRAF OCRDM FRC ICRA to D TCSR TIER TCR TOCR Output compare register A B 16 bits Output compare register AR AF 16 bits Output compare register 16 bits F...

Page 343: ...t capture D input pin FTID Input Input capture D input 12 3 Register Descriptions The FRT has the following registers Free running counter FRC Output compare register A OCRA Output compare register B...

Page 344: ...it units cannot be accessed in 8 bit units OCR is initialized to H FFFF 12 3 3 Input Capture Registers A to D ICRA to ICRD The FRT has four input capture registers ICRA to ICRD each of which is a 16 b...

Page 345: ...addition function do not select internal clock 2 as the FRC input clock together with a set value of H 0001 or less for OCRAR or OCRAF OCRAR and OCRAF should always be accessed in 16 bit units cannot...

Page 346: ...in TCSR is set to 1 0 ICIB requested by ICFB is disabled 1 ICIB requested by ICFB is enabled 5 ICICE 0 R W Input Capture Interrupt C Enable Selects whether to enable input capture interrupt C request...

Page 347: ...set to 1 0 FOVI requested by OVF is disabled 1 FOVI requested by OVF is enabled 0 0 R Reserved This bit is always read as 0 and cannot be modified 12 3 7 Timer Control Status Register TCSR TCSR is us...

Page 348: ...ture signal When BUFEA 1 on occurrence of an input capture signal specified by the IEDGC bit at the FTIC input pin ICFC is set but data is not transferred to ICRC In buffer operation ICFC can be used...

Page 349: ...cates that the FRC value matches the OCRB value Setting condition When FRC OCRB Clearing condition Read OCFB when OCFB 1 then write 0 to OCFB 1 OVF 0 R W Overflow Flag This status flag indicates that...

Page 350: ...on the falling edge of FTIB 1 Capture on the rising edge of FTIB 5 IEDGC 0 R W Input Edge Select C Selects the rising or falling edge of the input capture C signal FTIC 0 Capture on the falling edge...

Page 351: ...ICRDMS 0 R W Input Capture D Mode Select Specifies whether ICRD is used in the normal operating mode or in the operating mode using OCRDM 0 The normal operating mode is specified for ICRD 1 The opera...

Page 352: ...t is enabled 2 OEB 0 R W Output Enable B Enables or disables output of the output compare B output pin FTOB 0 Output compare B output is disabled 1 Output compare B output is enabled 1 OLVLA 0 R W Out...

Page 353: ...4 1 Pulse Output Figure 12 2 shows an example of 50 duty pulses output with an arbitrary phase difference When a compare match occurs while the CCLRA bit in TCSR is set to 1 the OLVLA and OLVLB bits a...

Page 354: ...the increment timing with an external clock source The pulse width of the external clock signal must be at least 1 5 system clocks The counter will not increment correctly if the pulse width is short...

Page 355: ...LVL bit in TOCR is output at the output compare pin FTOA or FTOB Figure 12 5 shows the timing of this operation for compare match A FRC OCRA N N N 1 N 1 N N Compare match A signal OLVLA Output compare...

Page 356: ...e timing when the rising edge is selected Input capture input pin Input capture signal Figure 12 7 Input Capture Input Signal Timing Usual Case If ICRA to ICRAD are read when the corresponding input c...

Page 357: ...M n M N n Figure 12 9 Buffered Input Capture Timing Even when ICRC or ICRD is used as a buffer register its input capture flag is set by the selected transition of its input capture signal For example...

Page 358: ...of Input Capture Flag ICF Setting The input capture flag ICFA ICFB ICFC or ICFD is set to 1 by the input capture signal The FRC value is simultaneously transferred to the corresponding input capture r...

Page 359: ...two values match just before FRC increments to a new value When the FRC and OCRA or OCRB value match the compare match signal is not generated until the next cycle of the clock source Figure 12 12 sho...

Page 360: ...OVF Setting 12 5 9 Automatic Addition Timing When the OCRAMS bit in TOCR is set to 1 the contents of OCRAR and OCRAF are automatically added to OCRA alternately and when an OCRA compare match occurs a...

Page 361: ...is set by the input capture signal The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents and an FRC compare match Figure 12 15 shows the timing of setting the mask s...

Page 362: ...e 12 2 lists the sources and priorities of these interrupts The ICIA ICIB OCIA and OCIB interrupts can be used as the on chip DTC activation sources Table 12 2 FRT Interrupt Sources Interrupt Interrup...

Page 363: ...ar If an internal counter clear signal is generated during the state after an FRC write cycle the clear signal takes priority and the write is not performed Figure 12 17 shows the timing for this type...

Page 364: ...ment If an FRC increment pulse is generated during the state after an FRC write cycle the write takes priority and FRC is not incremented Figure 12 18 shows the timing for this type of conflict Addres...

Page 365: ...OCRAR and OCRAF to OCRA is selected and a compare match occurs in the cycle following the OCRA OCRAR and OCRAF write cycle the OCRA OCRAR and OCRAF write takes priority and the compare match signal i...

Page 366: ...FRC Operation When the internal clock is changed the changeover may cause FRC to increment This depends on the time at which the clock is switched bits CKS1 and CKS0 are rewritten as shown in table 1...

Page 367: ...ns of CKS1 and CKS0 Bits FRC Operation 1 Switching from low to low Clock before switchover Clock after switchover FRC clock FRC CKS bit rewrite N N 1 2 Switching from low to high Clock before switchov...

Page 368: ...286 0300 No Timing of Switchover by Means of CKS1 and CKS0 Bits FRC Operation 4 Switching from high to high Clock before switchover Clock after switchover FRC clock FRC N N 1 CKS bit rewrite N 2 Note...

Page 369: ...l clocks and an external clock Selection of three ways to clear the counters The counters can be cleared on compare match A or compare match B or by an external reset signal Timer output controlled by...

Page 370: ...omparator B_1 TCORB_1 TCSR_1 TCR_1 TMCI0 TMCI1 TCNT_0 Overflow 1 Overflow 0 Compare match B1 Compare match B0 TMO1 TMRI1 Select clock Control logic Internal bus Legend Interrupt signals Clear 0 2 8 64...

Page 371: ...elect clock Control logic Internal bus Legend Interrupt signals Clear Y TMR_X 2 4 TMR_Y 4 256 2048 CMIAX CMIBX OVIX CMIAY CMIBY OVIY ICIX TCORA_Y Time constant register A_Y TCORB_Y Time constant regis...

Page 372: ..._Y Timer output TMOY Output Output controlled by compare match Timer clock reset input TMIY ExTMIY Input External clock input TMCIY external reset input TMRIY for the counter TMR_X Timer output TMOX O...

Page 373: ...Y TCNT_Y Time constant register A_Y TCORA_Y Time constant register B_Y TCORB_Y Timer control register_Y TCR_Y Timer control status register_Y TCSR_Y Timer input select register TISR TMR_X Timer counte...

Page 374: ...cess TCORA is continually compared with the value in TCNT When a match is detected the corresponding compare match flag A CMFA in TCSR is set to 1 Note however that comparison is disabled during the T...

Page 375: ...nabled or disabled when the CMFA flag in TCSR is set to 1 0 CMFA interrupt request CMIA is disabled 1 CMFA interrupt request CMIA is enabled 5 OVIE 0 R W Timer Overflow Interrupt Enable Selects whethe...

Page 376: ...0 1 1 0 Increments at falling edge of internal clock 1024 0 1 1 1 Increments at falling edge of internal clock 2048 TMR_1 1 0 0 Increments at compare match A from TCNT_0 TMR_Y 0 0 0 Disables clock inp...

Page 377: ...hen CMFB 1 then write 0 in CMFB 6 CMFA 0 R W Compare Match Flag A Setting condition When the values of TCNT_0 and TCORA_0 match Clearing condition Read CMFA when CMFA 1 then write 0 in CMFA 5 OVF 0 R...

Page 378: ...ese bits specify how the TMO0 pin output level is to be changed by compare match A of TCORA_0 and TCNT_0 00 No change 01 0 is output 10 1 is output 11 Output is inverted toggle output Note Only 0 can...

Page 379: ...cannot be modified 3 2 OS3 OS2 0 0 R W R W Output Select 3 2 These bits specify how the TMO1 pin output level is to be changed by compare match B of TCORB_1 and TCNT_1 00 No change 01 0 is output 10 1...

Page 380: ...FA 5 OVF 0 R W Timer Overflow Flag Setting condition When TCNT_X overflows from H FF to H 00 Clearing condition Read OVF when OVF 1 then write 0 in OVF 4 ICF 0 R W Input Capture Flag Setting condition...

Page 381: ...are Match Flag B Setting condition When the values of TCNT_Y and TCORB_Y match Clearing condition Read CMFB when CMFB 1 then write 0 in CMFB 6 CMFA 0 R W Compare Match Flag A Setting condition When th...

Page 382: ...Only 0 can be written for flag clearing 13 3 6 Input Capture Register TICR TICR is an 8 bit register The contents of TCNT are transferred to TICR at the rising edge of the external reset input TICR c...

Page 383: ...R and TICRF are initialized to H 00 The TICRR and TICRF functions are used for timer connection For details see section 14 Timer Connection 13 3 9 Timer Input Select Register TISR TISR selects a signa...

Page 384: ...rding to the compare match of TCORA and then set the CCLR0 bit to 1 2 Set the OS3 to OS0 bits in TCSR to B 0110 so that 1 is output according to the compare match of TCORA and 0 is output according to...

Page 385: ...nal clock source The pulse width of the external clock signal must be at least 1 5 system clocks for a single edge and at least 2 5 system clocks for both edges The counter will not increment correctl...

Page 386: ...nd TCOR match the compare match signal is not generated until the next TCNT input clock Figure 13 6 shows the timing of CMF flag setting TCNT N N 1 TCOR N Compare match signal CMF Figure 13 6 Timing o...

Page 387: ...ompare match N H 00 Compare match signal TCNT Figure 13 8 Timing of Counter Clear by Compare Match 13 5 5 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input depen...

Page 388: ...EJ09B0286 0300 13 5 6 Timing of Overflow Flag OVF Setting The OVF bit in TCSR is set to 1 when the TCNT overflows changes from H FF to H 00 Figure 13 10 shows the timing of OVF flag setting OVF Overfl...

Page 389: ...ar specification If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match the 16 bit counter TCNT_0 and TCNT_1 together is cleared when a 16 bit compare match occurs The 1...

Page 390: ...etected while the ICST bit is set to 1 the value of TCNT_X at that time is transferred to both TICRR and TICRF and the ICST bit is cleared to 0 The TMRIX input signal can be switched by the setting of...

Page 391: ...Signal Input TMRIX input capture input signal of TMR_X is switched according to the setting of the bits in TCONRI of the timer connection Input capture signal selections are shown in figure 13 13 and...

Page 392: ...on 1 1 0 TMCI1 pin input selection 1 Inverted TMCI1 pin input selection Legend Don t care 13 8 Interrupt Sources TMR_0 TMR_1 and TMR_Y can generate three types of interrupts CMIA CMIB and OVI TMR_X ca...

Page 393: ...compare match CMFA Possible CMIB0 TCORB_0 compare match CMFB Possible OVI0 TCNT_0 overflow OVF Not possible TMR_1 CMIA1 TCORA_1 compare match CMFA Possible CMIB1 TCORB_1 compare match CMFB Possible OV...

Page 394: ...tween TCNT Write and Clear 13 9 2 Conflict between TCNT Write and Increment If a TCNT input clock is generated during the T2 state of a TCNT write cycle as shown in figure 13 15 the write takes priori...

Page 395: ...s priority and the compare match signal is disabled With TMR_X a TICR input capture conflicts with a compare match in the same way as with a write to TCORC In this case also the input capture takes pr...

Page 396: ...nal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over Table 13 6 shows the relationship between the timing at which the internal clock is switched by wr...

Page 397: ...Operation 1 Clock switching from low to low level 1 Clock before switchover Clock after switchover TCNT clock TCNT CKS bit rewrite N N 1 2 Clock switching from low to high level 2 Clock before switch...

Page 398: ...itching from low to stop and from stop to low 2 Includes switching from stop to high 3 Includes switching from high to stop 4 Generated on the assumption that the switchover is a falling edge TCNT is...

Page 399: ...inversion Positive logic is assumed for all signals used within the timer connection facility An edge detection circuit is connected to the input pins simplifying signal input detection TMR_X can be u...

Page 400: ...TMO1 TMO1 output selection B FRT output selection B IHO signal selection CL4 generation CL4 signal CLAMPO FTIC CLO signal selection PDC signal PWM decoding 8 bit TMR_X CMB TMO CMA ICR ICR 1C compare m...

Page 401: ...BACKI Input Spare vertical synchronization signal input pin or FTIB input pin Spare horizontal synchronization signal input pin HFBACKI Input Spare horizontal synchronization signal input pin or FTCI...

Page 402: ...nput Synchronization Mode Select 1 0 These bits select the signal source of the IHI and IVI signals Mode 00 No signal 01 S on G mode 10 Composite mode 11 Separate mode IHI Signal 00 HFBACKI input 01 C...

Page 403: ...CRF can measure the width of a pulse by means of a single capture operation under the control of the ICST bit When a rising edge followed by a falling edge is detected on TMRIX after the ICST bit is s...

Page 404: ...gnal CSYNCI and the vertical synchronization signal VSYNCI HFINV 0 The HFBACKI pin state is used directly as the HFBACKI input 1 The HFBACKI pin state is inverted before use as the HFBACKI input VFINV...

Page 405: ...Initial value FTIA input FTIB input FTIC input FTID input TMI1 input TMI1 input 1 Synchronization signal connection mode IVI signal TMO1 signal VFBACKI input IHI signal IHI signal IVI inverse signal B...

Page 406: ...e of the relevant pin is determined by port DR and DDR FRT TMR and PWM settings Output enabling disabling control does not affect the port FRT or TMR input functions but some FRT and TMR input signal...

Page 407: ...PO and the blanking waveform CBLANK HOINV 0 The IHO signal is used directly as the HSYNCO output 1 The IHO signal is inverted before use as the HSYNCO output VOINV 0 The IVO signal is used directly as...

Page 408: ...TMR_Y registers are accessed at addresses H FF FFF0 to H FF FFF5 6 ISGENE 0 R W Internal Synchronization Signal Selects internal synchronization signals IHG IVG and CL4 signals as the signal sources...

Page 409: ...tion is selected 11 The IVI signal with fall modification and IHI synchronization is selected ISGENE 1 XX The IVG signal is selected 1 0 CLMOD1 CLMOD0 0 0 R W R W Clamp Waveform Mode Select 1 0 These...

Page 410: ...ion When a rising edge is detected on the VSYNCI pin 6 HEDG 0 R W 1 HSYNCI Edge Detects a rising edge on the HSYNCI pin Clearing condition When 0 is written in HEDG after reading HEDG 1 Setting condit...

Page 411: ...ition When an IHI signal 2fH modification condition is detected 1 IHI Undefined 2 R IHI Signal Level Indicates the current level of the IHI signal Signal source and phase inversion selection for the I...

Page 412: ...the result of the pulse width decision at the first compare match signal B timing after TCNT is reset by the rise of the IHI signal is output as the PDC signal The pulse width setting using TICRR and...

Page 413: ...ignals can be specified by TCORA The rise of the CL3 signal can be specified as simultaneous with the sampling of the fall of the IHI signal using the system clock and the fall of the CL3 signal can b...

Page 414: ...ignals is synchronized with the edge of the IHI signal and their fall is synchronized with the system clock the pulse width variation is equivalent to the resolution of the system clock Both the rise...

Page 415: ...carried out efficiently To measure the period of an IHI signal divided waveform TCNT in TMR_1 is set to count the external clock IHI signal pulses and to be cleared on the rising edge of the external...

Page 416: ...nted on the rising edge of the external clock IHI signal TCSR in TMR_1 3 to 0 OS3 to OS0 0011 Not changed by compare match B output inverted by compare match A toggle output Division by 512 1001 When...

Page 417: ...nts can be added automatically to the data captured in ICRD in the FRT and compare matches generated at these points The interval between the two compare matches is called a mask interval A value equi...

Page 418: ...re input D IHI signal 1 0 CKS1 CKS0 01 FRC is incremented on internal clock 8 TCSR in FRT 0 CCLRA 0 FRC clearing is disabled TOCR in FRT 7 ICRDMS 1 ICRD is set to the operating mode in which OCRDM is...

Page 419: ...external reset signal inverse of the IVI signal The number of IHI signal pulses until the fall of the IVI signal is written in TCORB Since the IVI signal supplied to the IVO signal selection circuit...

Page 420: ...ernal clock IHI signal TCSR in TMR_1 3 to 0 OS3 to OS0 0011 Not changed by compare match B output inverted by compare match A toggle output 1001 When TCORB TCORA 1 output on compare match B 0 output o...

Page 421: ...interval of the IVG signal is written in OCRAR and a value corresponding to the 1 interval of the IVG signal is written in OCRAF The IVG signal is set by a compare match after an OCRAR addition and r...

Page 422: ...2 to CKS0 001 TCNT is incremented on internal clock 4 TCSR in TMR_Y 3 to 0 OS3 to OS0 0110 0 output on compare match B 1 output on compare match A TCORA in TMR_Y H 3F example IHG signal period 256 TCO...

Page 423: ...2 REJ09B0286 0300 6 system clocks 6 system clocks 6 system clocks OCRA 4 OCRA 3 OCRAR OCRA 3 OCRA 2 OCRAF OCRA 2 OCRA 1 OCRAR OCRA 1 OCRA 0 OCRAF OCRA FRC CL4 signal IHG signal TCORA TCORB TCNT IVG si...

Page 424: ...ncy part of CSYNCI input composite synchronization signal is eliminated before output CL1 signal CSYNCI input composite synchronization signal horizontal synchronization signal part is separated befor...

Page 425: ...ified and signal is synchronized with HFBACKI input before output IVG signal Internal synchronization signal is output S on G mode or composite mode PDC signal IVI signal without fall modification or...

Page 426: ...HI synchronization VSYNCI input vertical synchronization signal fall is modified and signal is synchronized with HSYNCI input horizontal synchronization signal before output IVG signal Internal synchr...

Page 427: ...T can be used as an interval timer In interval timer operation an interval timer interrupt is generated each time the counter overflows A block diagram of the WDT is shown in figure 15 1 15 1 Features...

Page 428: ...NT_0 Timer counter_0 TCSR_1 Timer control status register_1 TCNT_1 Timer counter_1 Notes 1 The RESO signal outputs the low level signal when the internal reset signal is generated due to a TCNT overfl...

Page 429: ...criptions The WDT has the following registers To prevent accidental overwriting TCSR and TCNT have to be written to in a method different from normal registers For details see section 15 6 1 Notes on...

Page 430: ...F is cleared automatically by the internal reset Clearing conditions When TCSR is read when OVF 1 then 0 is written to OVF When 0 is written to TME 6 WT IT 0 R W Timer Mode Select Selects whether the...

Page 431: ...Select 2 to 0 Selects the clock source to be input to The overflow frequency for 25 MHz is enclosed in parentheses 000 2 frequency 20 4 s 001 64 frequency 655 3 s 010 128 frequency 1 3 ms 011 512 fre...

Page 432: ...n to OVF When 0 is written to TME 6 WT IT 0 R W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer 0 Interval timer mode 1 Watchdog timer mode 5 TME 0 R W Timer En...

Page 433: ...1 3 ms 010 SUB 8 cycle 62 5 ms 011 SUB 16 cycle 125 ms 100 SUB 32 cycle 250 ms 101 SUB 64 cycle 500 ms 110 SUB 128 cycle 1 s 111 256 cycle 2 s Notes 1 Only 0 can be written to clear the flag 2 When OV...

Page 434: ...tatus in SYSCR If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow the RES pin reset has priority and the XRST bit in SYSCR is set to 1 An NM...

Page 435: ...be generated at intervals When the TCNT overflows in interval timer mode an interval timer interrupt WOVI is requested at the same time the OVF bit of TCSR is set to 1 The timing is shown figure 15 4...

Page 436: ...ates Overflow signal internal signal OVF RESO signal Internal reset signal Figure 15 5 Output Timing of RESO RESO RESO RESO Signal 15 5 Interrupt Sources During interval timer mode operation an overfl...

Page 437: ...CSR both have the same write address Therefore satisfy the relative condition shown in figure 15 6 to write to TCNT or TCSR To write to TCNT the higher bytes must contain the value H 5A and the lower...

Page 438: ...data Figure 15 7 Conflict between TCNT Write and Increment 15 6 3 Changing Values of CKS2 to CKS0 Bits If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating errors could occur in the...

Page 439: ...e and sub active or watch mode the counter does not display the correct value due to internal clock switching Specifically when transiting from high speed mode to sub active or watch mode that is when...

Page 440: ...Section 15 Watchdog Timer WDT Rev 3 00 Jan 25 2006 page 386 of 872 REJ09B0286 0300...

Page 441: ...data transfers are secured using the internal cyclic redundancy check CRC operation circuit Since the CRC operation circuit is not connected to the SCI data is transferred to the circuit using the MOV...

Page 442: ...selectable at 16 or 24 MHz operation and 230 392 kbps or 115 196 kbps selectable at 20 MHz operation Clocked Synchronous Mode Data length 8 bits Receive error detection Overrun errors SCI channel sel...

Page 443: ...rate generator BRR Module data bus RDR TSR RSR Parity generation Parity check Legend RSR Receive shift register RDR Receive data register TSR Transmit shift register TDR Transmit data register SMR Ser...

Page 444: ...r Serial status register Smart card mode register Bit rate register Serial enhanced mode register Serial RFU enable register SCMR SSR SCR SMR SEMR SCIDTER Transmission reception control Baud rate gene...

Page 445: ...put Channel 2 receive data input TxD2 Output Channel 2 transmit data output 2 SSE2I Input Channel 2 stop input Note Pin names SCK RxD and TxD are used in the text for all channels omitting the channel...

Page 446: ...s way continuous receive operations be performed After confirming that the RDRF bit in SSR is set to 1 read RDR for only once RDR cannot be written to by the CPU 16 3 3 Transmit Data Register TDR TDR...

Page 447: ...as the data length LSB first is fixed and the MSB of TDR is not transmitted in transmission In clocked synchronous mode a fixed data length of 8 bits is used 5 PE 0 R W Parity Enable enabled only in a...

Page 448: ...9 Bit Rate Register BRR n is the decimal display of the value of n in BRR see section 16 3 9 Bit Rate Register BRR Bit Functions in Smart Card Interface Mode When SMIF in SCMR 1 Bit Bit Name Initial...

Page 449: ...asic clock cycles in a 1 bit data transfer time in smart card interface mode 00 32 clock cycles S 32 01 64 clock cycles S 64 10 372 clock cycles S 372 11 256 clock cycles S 256 For details see section...

Page 450: ...I interrupt request is enabled 6 RIE 0 R W Receive Interrupt Enable When this bit is set to 1 RXI and ERI interrupt requests are enabled 5 TE 0 R W Transmit Enable When this bit is set to 1 transmissi...

Page 451: ...ck source and SCK pin function Asynchronous mode 00 Internal clock SCK pin functions as I O port 01 Internal clock Outputs a clock of the same frequency as the bit rate from the SCK pin 1X External cl...

Page 452: ...MP bit in SMR is 1 in asynchronous mode Write 0 to this bit in smart card interface mode 2 TEIE 0 R W Transmit End Interrupt Enable Write 0 to this bit in smart card interface mode 1 0 CKE1 CKE0 0 0 R...

Page 453: ...ding TDRE 1 When a TXI interrupt request is issued allowing DTC to write data to TDR When RFU is activated by TDRE 1 allowing data to be written to TDR only for SCI_0 and SCI_2 6 RDRF 0 R W Receive Da...

Page 454: ...en to FER after reading FER 1 In 2 stop bit mode only the first stop bit is checked 3 PER 0 R W Parity Error Setting condition When a parity error is detected during reception Clearing condition When...

Page 455: ...Functions in Smart Card Interface Mode When SMIF in SCMR 1 Bit Bit Name Initial Value R W Description 7 TDRE 1 R W Transmit Data Register Empty Indicates whether TDR contains transmit data Setting co...

Page 456: ...from RDR When RFU is activated by RDRF 1 allowing data to be read from RDR only for SCI_0 and SCI_2 The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0...

Page 457: ...nsmission start When GM 0 and BLK 1 1 5 etu after transmission start When GM 1 and BLK 0 1 0 etu after transmission start When GM 1 and BLK 1 1 0 etu after transmission start Clearing conditions When...

Page 458: ...t is valid only when the 8 bit data format is used for transmission reception when the 7 bit data format is used data is always transmitted received with LSB first 2 SINV 0 R W Smart Card Data Invert...

Page 459: ...100 Clocked synchronous mode B Smart card interface mode B Error B S 22n 1 N 1 106 1 100 8 22n 1 N 1 106 S 22n 1 N 1 106 Notes B Bit rate bit s N BRR setting for baud rate generator 0 N 255 Operating...

Page 460: ...0 00 0 19 2 34 9600 0 6 2 48 0 7 0 00 0 9 2 34 19200 0 3 0 00 0 4 2 34 31250 0 1 0 00 0 2 0 00 38400 0 1 0 00 Operating Frequency MHz 3 6864 4 4 9152 5 Bit Rate bit s n N Error n N Error n N Error n N...

Page 461: ...0 11 0 00 0 12 0 16 31250 0 5 0 00 0 5 2 40 0 7 0 00 38400 0 4 2 34 0 4 0 00 0 5 0 00 Operating Frequency MHz 9 8304 10 12 12 288 Bit Rate bit s n N Error n N Error n N Error n N Error 110 2 174 0 26...

Page 462: ...0 16 0 27 0 00 31250 0 13 0 00 0 14 1 70 0 15 0 00 0 16 1 20 38400 0 11 0 00 0 12 0 16 0 16 0 00 Operating Frequency MHz 18 19 6608 20 25 Bit Rate bit s n N Error n N Error n N Error n N Error 110 3 7...

Page 463: ...0 0 6 144 192000 0 0 19 6608 614400 0 0 7 3728 230400 0 0 20 625000 0 0 8 250000 0 0 25 781250 0 0 Table 16 5 Maximum Bit Rate with External Clock Input Asynchronous Mode MHz External Input Clock MHz...

Page 464: ...0 159 0 199 0 249 50k 0 9 0 19 0 39 0 49 0 79 0 99 0 124 100k 0 4 0 9 0 19 0 24 0 39 0 49 0 62 250k 0 1 0 3 0 7 0 9 0 15 0 19 0 24 500k 0 0 0 1 0 3 0 4 0 7 0 9 1M 0 0 0 1 0 3 0 4 2 5M 0 0 0 1 5M 0 0 L...

Page 465: ...0 00 0 1 30 0 1 25 0 1 8 99 Operating Frequency MHz 14 2848 16 0000 18 0000 20 0000 25 0000 Bit Rate bit s n N Error n N Error n N Error n N Error n N Error 9600 0 1 0 00 0 1 12 01 0 2 15 99 0 2 6 60...

Page 466: ...rCKS2 IrCKS1 IrCKS0 0 0 0 R W R W R W IrDA Clock Select 2 to 0 Specifies the high level width of the clock pulse during IrTxD output pulse encoding when the IrDA function is enabled 000 B x 3 16 three...

Page 467: ...in input 1 non selected state SCI_0 halts operation TxD0 high impedance state SCK0 fixed to high SCI_2 SSE2I pin input 0 selected state SCI_2 operates normally SSE2I pin input 1 non selected state SCI...

Page 468: ...lock frequency is 10 667 MHz operated using the basic clock with a frequency 16 times the transfer clock frequency 0010 Average transfer rate operation at 460 606 kbps when the system clock frequency...

Page 469: ...transfer clock frequency 1011 Average transfer rate operation at 230 392 kbps when the system clock frequency is 20 MHz operated using the basic clock with a frequency 16 times the transfer clock freq...

Page 470: ...Clearing condition When data transfer has been completed by activation of the RFU by TDRE 1 FIFO EMPTY SMIF 1 in SCMR and BLK 1 in SMR 0 Disables activation of the RFU by TEND 1 in SSR and does not m...

Page 471: ...goes to the space state low level recognizes a start bit and starts serial communication Inside the SCI the transmitter and receiver are independent units enabling full duplex communication Both the t...

Page 472: ...e 16 10 Serial Transfer Formats Asynchronous Mode PE 0 0 1 1 0 0 1 1 S 8 bit data STOP S 7 bit data STOP S 8 bit data STOP STOP S 8 bit data P STOP S 7 bit data STOP P S 8 bit data MPB STOP S 8 bit da...

Page 473: ...e of each bit as shown in figure 16 4 Thus the reception margin in asynchronous mode is determined by formula 1 below M 0 5 L 0 5 F 100 Formula 1 1 2N D 0 5 N M Reception margin N Ratio of bit rate to...

Page 474: ...E1 and CKE0 bits in SCR When an external clock is input at the SCK pin the clock frequency should be 16 times the bit rate used When the SCI is operated on an internal clock the clock can be output fr...

Page 475: ...operation can be specified by the ABCS bit in SEMR and is available for both clock sources of an internal clock generated by the on chip baud rate generator and an external clock input at the SCK pin...

Page 476: ...23 22 4 5 6 7 8 9 10 11 12 13 14 15 16 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 2 3 4 28 29 2 667 MHz 1 8424 MHz 1 bit Basic clock 16 Basic clock 10...

Page 477: ...ge transfer rate at basic clock 460 784 kbps Average tranfer rate 7 3725 MHz 16 460 784 kbps Average error rate 0 004 Average tranfer rate 5 76 MHz 8 720 kbps Average error rate 0 Average transfer rat...

Page 478: ...be supplied even during initialization Wait Initialization completion Start initialization Set data transfer format in SMR and SCMR 1 Set CKE1 and CKE0 bits in SCR TE and RE bits are 0 No Yes Set val...

Page 479: ...wing order start bit transmit data parity bit or multiprocessor bit may be omitted depending on the format and stop bit 4 The SCI checks the TDRE flag at the timing for sending the stop bit 5 If the T...

Page 480: ...is enabled 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmission continuation...

Page 481: ...ansferred to RDR If the RIE bit in SCR is set to 1 at this time an ERI interrupt request is generated 4 If a framing error when the stop bit is 0 is detected the FER bit in SSR is set to 1 and receive...

Page 482: ...FER PER and RDRF bits to 0 before resuming reception Figure 16 12 shows a sample flow chart for serial data reception Table 16 11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF ORER...

Page 483: ...te error processing ensure that the ORER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 In the case of a framing error a break can be detected by...

Page 484: ...of 872 REJ09B0286 0300 End 3 Error processing Parity error processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER 1 FER...

Page 485: ...code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added It then sends transmit data as data with a 0 multiprocessor bit added The r...

Page 486: ...ssion to receiving station specified by ID MPB 1 MPB 0 H 01 H AA Legend MPB Multiprocessor bit Figure 16 13 Example of Communication Using Multiprocessor Format Transmission of Data H AA to Receiving...

Page 487: ...o TDR Set the MPBT bit in SSR to 0 or 1 Finally clear the TDRE flag to 0 3 Serial transmission continuation procedure To continue serial transmission be sure to read 1 from the TDRE flag to confirm th...

Page 488: ...r interrupt generated Idle state mark state RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine If not this station s ID MPIE bit is set to 1 again RXI interrupt request is...

Page 489: ...ception and comparison Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and compare it with this station s ID If the data is not this station s ID set the MPIE bit t...

Page 490: ...06 page 436 of 872 REJ09B0286 0300 End Error processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER 1 FER 1 Break Clear RE bit...

Page 491: ...previous receive data can be read during reception enabling continuous data transfer Don t care Don t care One unit of transfer data character or frame Bit 0 Serial data Synchronization clock Bit 1 Bi...

Page 492: ...in SMR and SCMR 3 Write a value corresponding to the bit rate to BRR This step is not necessary if an external clock is used 4 Wait at least one bit interval then set the TE bit or RE bit in SCR to 1...

Page 493: ...R to TSR and serial transmission of the next frame is started 6 If the TDRE flag is set to 1 the TEND flag in SSR is set to 1 and the TxD pin maintains the output state of the last bit If the TEIE bit...

Page 494: ...d as the transmit data output pin 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial tra...

Page 495: ...lag remains to be set to 1 3 If reception finishes successfully the RDRF bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an RXI interrupt r...

Page 496: ...read the ORER flag in SSR and after performing the appropriate error processing clear the ORER flag to 0 Transfer cannot be resumed if the ORER flag is set to 1 4 SCI status check and receive data re...

Page 497: ...o 0 Then after checking that the RDRF bit in SSR and receive error flags ORER FER and PER are cleared to 0 simultaneously set the TE and RE bits to 1 with a single instruction 16 6 6 SCI Selection in...

Page 498: ...smission reception cannot be resumed if the ORER flag is set to 1 4 SCI status check and receive data read Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and clear...

Page 499: ...As in the figure since this LSI communicates with the IC card using a single transmission line interconnect the TxD and RxD pins and pull up the data transmission line to VCC using a resistor Setting...

Page 500: ...or 1 etu after 10 5 etu has passed from the start bit If an error signal is sampled during transmission the same data is automatically re transmitted after two or more etu Ds D0 D1 D2 D3 D4 D5 D6 D7 D...

Page 501: ...vert the parity bit in both transmission and reception 16 7 3 Block Transfer Mode Block transfer mode is different from normal smart card interface mode in the following respects If a parity error is...

Page 502: ...margin N Ratio of bit rate to clock N 32 64 372 256 D Clock duty D 0 to 1 0 L Frame length L 10 F Absolute value of clock rate deviation Assuming values of F 0 D 0 5 and N 372 in formula 1 the recepti...

Page 503: ...e corresponding to the bit rate in BRR 6 Set the CKE1 and CKE0 bits in SCR appropriately Clear the TIE RIE TE RE MPIE and TEIE bits to 0 simultaneously When the CKE0 bit is set to 1 the SCK pin is all...

Page 504: ...Writing transmit data to TDR starts transmission of the next data Figure 16 31 shows a sample flowchart for transmission All the processing steps are automatically performed using a TXI interrupt requ...

Page 505: ...frorm TDR to TSR Transfer from TDR to TSR Transfer from TDR to TSR 2 4 3 Figure 16 29 Data Re transfer Operation in SCI Transmission Mode Note that the TEND flag is set in different timings depending...

Page 506: ...REJ09B0286 0300 Initialization No Yes Clear TE bit in SCR to 0 Start transmission Start No No No Yes Yes Yes Yes No End Write data to TDR and clear TDRE flag in SSR to 0 Error processing Error proces...

Page 507: ...uest to activate the DTC In reception setting the RIE bit to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1 This activates DTC by an RXI request thus allowing transfe...

Page 508: ...nd Error processing No No No Yes Yes ORER 0 and PER 0 RDRF 1 All data received Yes Figure 16 33 Sample Reception Flowchart 16 7 8 Clock Output Control Clock output can be fixed using the CKE1 and CKE0...

Page 509: ...the CKE0 bit in SCR to 1 to start clock output At Transition from Smart Card Interface Mode to Software Standby Mode 1 Set the port data register DR and data direction register DDR corresponding to t...

Page 510: ...the system defined by the IrDA standard version 1 0 In the system defined by the IrDA standard version 1 0 communication is started at a transfer rate of 9600 bps which can be modified as required Th...

Page 511: ...1 6 s to 3 16 bit cycle Start bit Stop bit Stop bit Start bit Figure 16 37 IrDA Transmission and Reception Reception During reception IR frames are converted to UART frames using the IrDA interface be...

Page 512: ...011 011 011 011 4 9152 011 011 011 011 011 011 5 011 011 011 011 011 011 6 100 100 100 100 100 100 6 144 100 100 100 100 100 100 7 3728 100 100 100 100 100 100 8 100 100 100 100 100 100 9 8304 100 10...

Page 513: ...atically cleared to 0 at data transfer by the DTC When the RDRF flag in SSR is set to 1 an RXI interrupt request is generated When the ORER PER or FER flag in SSR is set to 1 an ERI interrupt request...

Page 514: ...F Possible TXI2 Transmit data empty TDRE Possible 2 TEI2 Transmit end TEND Not possible Low 16 9 2 Interrupts in Smart Card Interface Mode Table 16 14 shows the interrupt sources in smart card interfa...

Page 515: ...s see section 7 Data Transfer Controller DTC In reception an RXI interrupt request is generated when the RDRF flag in SSR is set to 1 This activates the DTC by an RXI interrupt request thus allowing t...

Page 516: ...ode Only Transmission cannot be started when a receive error flag ORER FER or RER in SSR is set to 1 even if the TDRE flag in SSR is cleared to 0 Be sure to clear the receive error flags to 0 before s...

Page 517: ...to TDR clear TDRE in this order and then start transmission To transmit data in a different transmission mode initialize the SCI first Figure 16 39 shows a sample flowchart for mode transition during...

Page 518: ...ring TDRE to 0 after mode cancellation however if the DTC has been initiated the data remaining in DTC RAM will be transmitted when TE and TIE are set to 0 2 Also clear TIE and TEIE to 0 when they are...

Page 519: ...SCI TxD output Last TxD bit retained Note Initialized in software standby mode Figure 16 41 Pin States during Transmission in Clocked Synchronous Mode Internal Clock Start reception Reception 1 No No...

Page 520: ...ut Bit 6 Bit 7 Low pulse of half a cycle Figure 16 43 Switching from SCK Pins to Port Pins To prevent the low pulse output that is generated when switching the SCK pins to the port pins specify the SC...

Page 521: ...parallel One of three generating polynomials selectable CRC code generation for LSB first or MSB first communication selectable Figure 16 45 shows a block diagram of the CRC operation circuit Interna...

Page 522: ...mmunication The upper byte bits 15 to 8 is first transmitted when CRCDOR contents CRC code are divided into two bytes to be transmitted in two parts 1 0 G1 G0 0 0 R W R W CRC Generating Polynomial Sel...

Page 523: ...CRCDORL CRC code generation 2 Write H F0 to CRCDIR 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 CRC code H F78F CRC code Output Data 3 Read from CRCDOR 7 7 7 F F F 0 8 7 0 0 0 4 Serial transmissio...

Page 524: ...DIR 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 CRCDIR CRCDORH CRCDORL CRC code generation 4 Write H 8F to CRCDIR 1 7 0 0 0 1 1 0 7 0 7 0 7 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 CRCDIR CRCDORH CRC...

Page 525: ...DIR 1 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 CRCDIR CRCDORH CRCDORL CRC code generation 4 Write H EF to CRCDIR 1 7 1 1 0 1 1 0 7 0 7 0 7 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 CRCDIR CRCDORH CRC...

Page 526: ...ission and MSB first transmission CRCDIR CRCDORH CRCDORL 1 CRC code generation 2 Transmission data i LSB first transmission CRC code generation After specifying the operation method write data to CRCD...

Page 527: ...owledge output levels when receiving For I2 C bus format automatic loading of acknowledge bit when transmitting For I2 C bus format wait bit function in master mode A wait can be inserted by driving t...

Page 528: ...MOS open drain outputs when the bus drive function is selected Operation using the operation reservation adapter Figure 17 1 shows a block diagram of the I2 C bus interface Figure 17 2 shows an exampl...

Page 529: ...Second slave address register IIC operation reservation adapter count register IIC operation reservation adapter control register IIC operation reservation adapter command register Internal data bus...

Page 530: ...Function SCL0 Input Output Clock input output pin of channel 0 0 SDA0 Input Output Data input output pin of channel 0 SCL1 Input Output Clock input output pin of channel 1 1 SDA1 Input Output Data inp...

Page 531: ...RE and ICDRF When ICDRE is 1 and the transmit buffer is empty ICDRE shows that the next transmit data can be written from the CPU When ICDRF is 1 it shows that valid receive data is stored in the rece...

Page 532: ...the shift register Data transfer from the transmit buffer to the shift register if the shift register is empty when ICDRE 0 in transmit mode Do not write to ICDR in receive mode because the ICDRE flag...

Page 533: ...ster when ICDRF 0 in receive mode Data is not transferred from the shift register to the receive buffer in transmit mode To read data in the shift register read ICDR in receive mode Clearing condition...

Page 534: ...ter a start condition the LSI operates as the slave device specified by the master device SAR can be accessed only when the ICE bit in ICCR is cleared to 0 Bit Bit Name Initial Value R W Description 7...

Page 535: ...he master device SARX can be accessed only when the ICE bit in ICCR is cleared to 0 Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 0 0 0 0 0 0 0 R W...

Page 536: ...n master mode with the I 2 C bus format 0 Data and the acknowledge bit are transferred consecutively with no wait inserted 1 After the fall of the clock for the final data bit the IRIC flag is set to...

Page 537: ...Bit BC2 to BC0 settings should be made during an interval between transfer frames If bits BC2 to BC0 are set to a value other than B 000 the setting should be made while the SCL line is low The value...

Page 538: ...160 kHz 200 kHz 240 kHz 0 112 44 6 kHz 71 4 kHz 89 3 kHz 107 kHz 143 kHz 179 kHz 214 kHz 0 1 1 1 128 39 1 kHz 62 5 kHz 78 1 kHz 93 8 kHz 125 kHz 156 kHz 188 kHz 0 56 89 3 kHz 143 kHz 179 kHz 212 kHz 2...

Page 539: ...e Initial Value R W Description 7 ICE 0 R W I 2 C Bus Interface Enable 0 This module is stopped and disconnected from the SCL and SDA pins SAR and SARX can be accessed 1 This module can perform transf...

Page 540: ...When the TRS bit is intended to change during a transfer the bit will not be switched until data transfer ends MST clearing conditions 1 When 0 is written by software 2 When lost in bus conflict in I...

Page 541: ...tion Prohibit In master mode Writing 0 in BBSY and 0 in SCP A stop condition is issued Writing 1 in BBSY and 0 in SCP A start condition and a restart condition are issued In slave mode Writing to the...

Page 542: ...of data transfer rise of the 9th transmit receive clock without no waits When a slave address is received after bus arbitration is lost first frame after start condition If 1 is received as the acknow...

Page 543: ...r details see the description of the DTC operation given below Note Only 0 can be written to clear the flag When the DTC is used the IRIC flag is cleared automatically and transfer can be performed co...

Page 544: ...ondition is detected 1 1 1 0 0 1 0 0 0 0 0 1 Data transfer from transmit buffer to shift register automatic in above state 1 0 1 0 0 1 0 0 0 0 1 Reception end when previous state is ICDRF 0 1 0 1 0 0...

Page 545: ...0 2 0 0 0 0 1 Data transfer from transmit buffer to shift register automatic in above state 0 0 1 0 0 1 0 2 1 Reception end when previous state is ICDRF 0 0 0 1 0 0 0 0 0 0 Write to ICDR in above stat...

Page 546: ...ng frame transfer Clearing conditions When 0 is written in STOP after reading STOP 1 When the IRIC flag in ICCR is cleared to 0 5 IRTR 0 R W I 2 C Bus Interface Continuous Transfer Interrupt Request F...

Page 547: ...ndition is detected In master mode 3 AL 0 R W Arbitration Lost Flag Indicates that arbitration was lost in master mode Setting conditions When ALSL 0 If the internal SDA and SDA pin disagree at the ri...

Page 548: ...en to transmit mode or read from receive mode When 0 is written in AAS after reading AAS 1 In master mode 1 ADZ 0 R W General Call Address Recognition Flag In I 2 C bus format slave receive mode this...

Page 549: ...is read the value loaded from the bus line returned by the receiving device is read in transmission when TRS 1 In reception when TRS 0 the value set by internal software is read When this bit is writ...

Page 550: ...d SDA pins can drive the I 2 C bus similar to when the ICE bit in ICCR is set to 1 6 CRIC 0 R W Command Request Interrupt Enable Enables or disables the IIC operation reservation command execution end...

Page 551: ...bits of the conventional IIC module and the IIC operation reservation adapter must be initialized so as to deactivate the IIC module When bits 7 to 4 in this register are set cleared using a bit manip...

Page 552: ...th the I 2 C bus format This bit is automatically set by an operation reservation command 0 Data and the acknowledge bit are transferred consecutively with no wait inserted 1 After the fall of the clo...

Page 553: ...dition CREQ Generation Source Automatic command transition after slave address match ACKB 1 received NACK 1 when the acknowledge bit is enabled in transmit mode Stop condition detected STOPIMX 0 while...

Page 554: ...4 ABRT 0 R Abort 0 Normal end 1 Abort Clearing conditions When ICCMD is written to When 0 is written to ABRT after reading ABRT 1 Setting condition When a start stop condition is detected during data...

Page 555: ...sly the DERR value is ignored because this is normal operation and not an error When internal transmit data disagrees with the SDA pin level during transmission 1 TOVR 0 R W Timeover 0 Normal operatio...

Page 556: ...1 A transmit data write request is generated and an interrupt is requested in master mode Clearing conditions When ICDRX is written to When ICCMD is written to When 0 is written to MTREQ after reading...

Page 557: ...Setting condition When data transmission is completed in slave mode 4 SRREQ 0 R W 1 Slave Mode Receive Data Read Request Interrupt Flag 0 No receive data read request is generated in slave mode 1 A re...

Page 558: ...is not written to before the start condition is detected 2 When transfer of first frame address R W ends rise of 9th clock 2 When transmission of second or subsequent frames starts fall of 1st clock...

Page 559: ...en to or when data transmission ends rise of 9th clock with the next transmit data set in ICDRT TDRE 0 2 Clearing conditions in transmit mode When data transmission ends rise of 9th clock with the nex...

Page 560: ...9th clock When reception of second or subsequent frames ends fall of 8th clock 3 When ICDRX is read from with receive data in the shift register SDRF 1 in receive mode Clearing conditions When ICDRX i...

Page 561: ...ICDRX Rise of 9th clock in first frame in master mode Stop condition detected Stop condition detected Figure 17 3 State Transitions of TDRE SDRF and RDRF Bits 17 3 11 IIC Operation Reservation Adapter...

Page 562: ...3 IIC Operation Reservation Adapter Count Register ICCNT ICCNT controls monitoring of timeout related operations of the IIC operation reservation adapter Timeout Occurrence Condition In transmission r...

Page 563: ...rupt requests by stop conditions are disabled 5 4 CNTS1 CNTS0 0 0 R W R W Counter Select These bits specify the number of clock cycles for the timeout counter The clock is selected by the IICX1 and II...

Page 564: ...et to 1 ICCMD is automatically set to H A0 When the ICXE bit in ICCRX is cleared to 0 ICCMD is cleared to H 00 If a value not defined as an operation reservation command is written to ICCMD when the I...

Page 565: ...on of this bit is replaced by ICCMD The function of this bit can be monitored by the WAITX bit in ICSRA 5 to 3 CKS2 to CKS0 R W Select the transfer rate ICMR 2 to 0 BC2 to BC0 R W Set to B 000 9 bits...

Page 566: ...IIC data set consists of the first frame address read write and the subsequent frames data Each frame consists of 8 bit data and ACK NAK transmission of ACK or NAK and enabling or disabling NAK judgme...

Page 567: ...n receives using double buffer A8 AA Reserves slave transmission automatically stops at NAK reception Slave A9 AB Reserves slave transmission disables NAK AC to AF Reserved setting prohibited C0 to C3...

Page 568: ...3 Address reception Address reception completed AASX 1 R W 1 A8 to AB STREQ ICDRX read ACK transmitted reception completed SRREQ A4 ICDRX read ACK transmitted stop condition detected A0 CREQ ICDRX rea...

Page 569: ...C4 to C7 MRREQ C8 to CB ICDRX write Arbitration lost A0 CREQ ICDRX write Data transmission started MTREQ C8 NAK received CREQ C9 ICDRX write Transmission completed MTREQ ICDRX write Transmission compl...

Page 570: ...no acknowledge bit inserted The serial format is shown in figure 17 5 The I2 C bus timing is shown in figure 17 6 S A SLA 7 n R W DATA A 1 1 m 1 1 1 A A 1 P 1 Transfer bit count n 1 to 8 Transfer fram...

Page 571: ...etween generation of a start condition and output of data Although data H FF is to be sent to ICDR by a dummy write operation before an issue of a stop condition the H FF data may be output by the dum...

Page 572: ...clock pulse After one frame has been transmitted SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written 8 Read the ACKB bit in ICSR to confir...

Page 573: ...consists of ICDRR and ICDRS However if the completion of receiving the last data is delayed there will be a conflict between the instruction to issue a stop condition and the SCl clock output to recei...

Page 574: ...e 9th receive clock pulse to return an acknowledge signal 5 When one frame of data has been received the IRIC flag in ICCR and the IRTR flag in ICSR are set to 1 at the rise of the 9th receive clock p...

Page 575: ...vel of SDA is fixed as low 14 Clear the BBSY bit and SCP bit to 0 in ICCR This changes SDA from low to high when SCL is high and generates the stop condition SDA master output SDA slave output 2 1 2 1...

Page 576: ...d the MST and TRS bits in ICCR according to the operating mode 2 When the start condition output by the master device is detected the BBSY flag in ICCR is set to 1 3 When the slave address matches in...

Page 577: ...is detected the BBSY flag in ICCR is cleared to 0 SDA master output SDA slave output 2 1 2 1 4 3 6 5 8 7 9 Bit 7 Bit 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRIC ICDRS ICDRR RDRF SCL master...

Page 578: ...8 7 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 IRIC ICDRS ICDRR RDRF SCL master output SCL slave output Interrupt request generation Interrupt request generation Data 2 Data 2 Data...

Page 579: ...transferred to ICDRS and the TDRE internal flag and IRIC and IRTR flags are set to 1 again After clearing the IRIC flag to 0 write the next data to ICDR The slave device sequentially sends the data wr...

Page 580: ...Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRIC ICDRS ICDRT TDRE SCL master output Interrupt request generation Interrupt request generation Interrupt request generation Slave receive mode Slave transmit mode Dat...

Page 581: ...internal clock Figures 17 13 to 17 15 show the IRIC flag timings and SCL control and figure 17 16 shows an example of the interrupt flag timing of the operation reservation adapter When WAIT 0 while...

Page 582: ...ata transfer ends with ICDRE 0 for transmission or ICDRF 0 for reception SCL SDA IRIC User processing Clear IRIC Clear IRIC 8 8 9 1 1 A b Data transfer ends with ICDRE 1 for transmission or ICDRF 1 fo...

Page 583: ...ynchronous serial format b Data transfer ends with ICDRE 1 for transmission or ICDRF 1 for reception a Data transfer ends with ICDRE 0 for transmission or ICDRF 0 for reception Clear IRIC Clear IRIC W...

Page 584: ...CCMD 1 2 8 9 8 9 7 b Interrupt flag timing for request to read receive data in master or slave mode SCL MRREQ SRREQ Read from ICDRX Read from ICDRX 1 2 8 9 8 9 7 c Interrupt flag timing for request to...

Page 585: ...ledge bit value of 1 when the ACKE bit is 1 the DTC is not activated thus allowing an interrupt to be generated if enabled The acknowledge bit may indicate specific events such as completion of receiv...

Page 586: ...TC ICDR read Transmission by DTC ICDR write Reception by DTC ICDR read Dummy data H FF write Processing by DTC ICDR write Last frame processing Not necessary Reception by CPU ICDR read Not necessary R...

Page 587: ...sary Not necessary Not necessary Transfer request processing after last frame processing MTREQ Clearing by CPU CREQ Clearing by CPU MRREQ Clearing by CPU CREQ Clearing by CPU STREQ Clearing by CPU CRE...

Page 588: ...ion 17 3 7 IIC Operation Reservation Adapter Control Register ICCRX Scope of Initialization The initialization executed by this function covers the following items ICDRE and ICDRF internal flags Trans...

Page 589: ...eception is started again register initialization etc must be carried out as necessary to enable correct communication as a system The value of the BBSY bit cannot be modified directly by this module...

Page 590: ...iting to ICDR clear IRIC immediately 2 Test the status of the SCL and SDA lines 7 Wait for 1 byte to be transmitted 10 Wait for 1 byte to be transmitted 11 Test for end of tranfer 12 Stop condition is...

Page 591: ...r 1 byte to be received 13 Clear wait mode Read receive data Clear IRIC IRIC should be cleared to 0 after setting WAIT 0 14 Stop condition issuance 8 Wait for the data for the second and subsequent by...

Page 592: ...IRIC in ICCR IRIC 1 Clear IRIC in ICCR Set ACKB 1 in ICSR Read ICDR Read IRIC in ICCR Read ICDR IRIC 1 Clear IRIC in ICCR End General call address processing Description omitted Slave transmit mode 1...

Page 593: ...byte to be transmitted 3 Test for end of transfer 4 Set slave receive mode 5 Dummy read to release the SCL line Figure 17 21 Sample Flowchart for Slave Transmit Mode 17 6 Interrupt Sources The I2 C b...

Page 594: ...nterrupt request IRIC Possible SRIC Slave mode receive data read request interrupt SRREQ 0 IICT0 Slave mode transmit data write request interrupt STREQ Possible IICC1 CRIC Operation reservation comman...

Page 595: ...nd SDA outputs in synchronization with the internal clock Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance series resistance and parallel re...

Page 596: ...300 ns The I2 C bus interface SCL and SDA output timing is prescribed by tcyc as shown in table 17 11 However because of the rise and fall times the I2 C bus interface specifications may not be satisf...

Page 597: ...4080 tSTOSO 0 5 tSCLO 2 tcyc tSr High speed mode 300 600 1350 1200 1150 1075 1050 1030 Standard mode 1000 250 3100 3325 3400 3513 3550 3580 tSDASO master 1 tSCLLO 3 3 tcyc tSr High speed mode 300 100...

Page 598: ...the receive data ICDR data is read in the interval between execution of the instruction for issuance of the stop condition writing 0 to the BBSY bit in ICCR and the actual generation of the stop condi...

Page 599: ...tion 5 ICDR write transmit data 2 Determination of SCL Low 1 IRIC determination Start condition generation retransmission IRIC 1 Yes Clear IRIC in ICSR Read SCL pin Write transmit data to ICDR Set BBS...

Page 600: ...ures a high period SCL is detected as low because the rise of the waveform is delayed IH Figure 17 24 Stop Condition Issuance Timing 10 Note on IRIC flag clearing when wait function is used When the w...

Page 601: ...ing the time other than the shaded time Data transmission Bit 7 Address reception SCL TRS bit Waveform at problem occurrence ICDR read and ICCR read write are disabled Period of 6 system clocks 8 R W...

Page 602: ...be held low in some cases after transmit receive operation has been completed thus inconveniently allowing clock pulses to be output on the SCL bus line before ICDR is accessed correctly To access ICD...

Page 603: ...MR register to 1 and operating WAIT in master mode 2 If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock and the fall of the 8th clock b Error phenomenon Normall...

Page 604: ...ransition to slave receive mode is automatically carried out When arbitration is lost not in the first frame but in the second frame or subsequent frame transmit receive data that is not an address is...

Page 605: ...29 Diagram of Erroneous Operation when Arbitration Is Lost Though it is prohibited in the normal I2 C protocol the same problem may occur when the MST bit is erroneously set to 1 and a transition to...

Page 606: ...Section 17 I 2 C Bus Interface IIC Rev 3 00 Jan 25 2006 page 552 of 872 REJ09B0286 0300...

Page 607: ...B standard Rev 1 1 compliant USB function core executed by standard commands Executed by interpreting device class commands by the CPU Firmware must be created Compound function consisting of HID devi...

Page 608: ...size register 0S FIFO valid size register 01 FIFO valid size register 0I FIFO valid size register 1 FIFO valid size register 2 FIFO valid size register 3 Endpoint size register 1 RFU FIFO read reques...

Page 609: ...cket contains information relating to the device addresses and endpoints and transfer type A data packet contains data A handshake packet includes information relating to the transmission success or f...

Page 610: ...direction register 0 EPDIR0 Packet transfer enable register 0 PTTER0 USB interrupt enable register 0 USBIER0 USB interrupt enable register 1 USBIER1 USB interrupt flag register 0 USBIFR0 USB interrup...

Page 611: ...ket size of the data packet is equal to the FIFO size bytes EP0S is a specific FIFO for setup command reception which is enabled or disabled by the SETICNT bit in USBMDCR For details on RAM FIFOs that...

Page 612: ...es EPSZR1 is initialized to H 44 by a system reset or function software reset see section 18 3 16 USB Control Registers 0 and 1 USBCR0 USBCR1 Bit Bit Name Initial Value R W Description 7 6 5 4 EP1SZ3...

Page 613: ...function core according to the USB function core s request and then sent to the host Data sent to the host is stored in the FIFO by the USB function core and is enabled by returning an ACK handshake a...

Page 614: ...scription 7 to 0 D7 to D0 All 0 W Endpoint 3 is used for input transfer and EPDR3 is specified as a write only register 18 3 4 Endpoint Valid Size Registers 0S 0O 0I 1 2 and 3 FVSR0S FVSR0O FVSR0I FVS...

Page 615: ...of the data transfer can be checked by the DATA0 and DATA1 packet toggles If the DATA0 or DATA1 packet toggle is not performed correctly the USB function core stops the transaction processing and the...

Page 616: ...SR0OH H 00 FVSR0IH H 00 FVSR1H H 00 FVSR2H H 00 FVSR3H H 00 FVSR0SL FVSR0OL FVSR0IL FVSR1L FVSR2L FVSR3L Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 N7 N6 N5 N4 N3 N2 N1 N0 0 0 0 0 1 1...

Page 617: ...rols the data transfer direction of endpoint 5 0 Endpoint 5 is specified as host output transfer 1 Setting prohibited 5 EP4DIR 1 R W Endpoint 4 Data Direction Control Flag Controls the data transfer d...

Page 618: ...cket when it is not stalled or a NAK handshake if no data exists If an EPTE bit is set to 1 after the slave CPU has written the data that is to be transferred to the host in the FIFO the contents of F...

Page 619: ...s FVSR3 in endpoint 3 specific FIFO 3 EP2TE 0 R W Endpoint 2 Packet Transmission Enable Modifies FVSR2 for endpoint 2 if the EP2DIR bit is set to 1 0 Normal read value 1 Updates FVSR2 in endpoint 2 sp...

Page 620: ...tion core 4 SOFE 0 R W SOF Interrupt Enable 0 Disables USB function core SOF start of frame interrupt 1 Enables USB function core SOF start of frame interrupt 3 SPNDE 0 R W Suspend Interrupt Enable 0...

Page 621: ...IFR1 USBIFR0 and USBIFR1 have interrupt flags which generate interrupts from the USB module to the slave CPU The USB module supports four interrupt sources USBIA USBIB USBIC and USBID USBIA is specifi...

Page 622: ...nsfer Abnormal Completion Interrupt Status Indicates that data transfer for an USB core endpoint has been completed abnormally If the TFE bit in USBIER0 is set to 1 an USBID interrupt is requested to...

Page 623: ...atus Indicates that the USB function core detects an SOF Start of Frame by an up stream If the SOFE bit in USBIER0 is set to 1 an USBID interrupt is requested to the slave CPU Clearing condition 0 is...

Page 624: ...on from normal state to suspend state 0 SETUPF 0 R W Setup Interrupt Status The meaning of this bit differs depending on the SETICNT bit in USBMDCR When SETICNT 0 Indicates that endpoint 0 of the USB...

Page 625: ...icates that the USB function core detects a SetInterface command If the SETIE bit in USBIER1 is set to 1 an USBID interrupt is requested to the slave CPU Clearing condition 0 is written to after SETI...

Page 626: ...Clearing condition 0 is written to EP5TS after EP5TS 1 has been read 1 Indicates that the endpoint 5 host output transfer OUT transaction has been completed normally Setting condition An ACK handshake...

Page 627: ...ndition An ACK handshake has been achieved ACK reception after IN token reception and data transfer 3 EP2TS 0 R W Endpoint 2 Transfer Success Flag Indicates that the endpoint 2 host input output trans...

Page 628: ...ansaction has been completed normally Setting condition An ACK handshake has been achieved ACK reception after IN token reception and data transfer 1 EP0ITS 0 R W Endpoint 0 Transfer Success Flag Indi...

Page 629: ...d that cannot be processed in the USB core the EP0OTS flag is set to 1 Note that neither the EP0OTS nor the EP0OTF flag is set to 1 if the SEICNT bit in USBMDCR is set to 1 regardless of whether the c...

Page 630: ...etected if a NAK handshake has been received or a NAK handshake has been sent because no transfer data has been received FVSR FIFO size FIFO empty in host input transfer if a NAK handshake has been se...

Page 631: ...t be received because both receive buffers for RFU and FIFO become full after an OUT token has been received NAK transmission A communication error occurs after an OUT token has been received 5 EP4TF...

Page 632: ...O is empty after an IN token has been received NAK transmission 3 EP2TF 0 R W Endpoint 2 Transfer Failure Flag Indicates that the endpoint 2 host input or output transfer has been completed abnormally...

Page 633: ...en has been received and data has been transferred Data cannot be sent because the FIFO is empty after an IN token has been received NAK transmission 1 EP0ITF 0 R W Endpoint 0 Transfer Failure Flag In...

Page 634: ...o 1 Note that neither the EP0OTS nor the EP0OTF flag is set to 1 if the SEICNT bit in USBMDCR is set to 1 regardless of whether the command can be processed in the USB core or not 0 Indicates that the...

Page 635: ...be modified 3 EP0STOP 0 R W Endpoint 0 Stop Used to protect the contents of endpoint 0 FIFO in the USB function core Setting this bit to 1 protects the data that is sent to the EP0 OUT FIFO by a SETU...

Page 636: ...n software reset the USB function core has no endpoint information Endpoint information of the USB function core in this LSI can be set by writing to EPDR0I sequentially for details see section 18 4 7...

Page 637: ...OUT FIFO contents If the received command cannot be processed in the USB function core the EP0OTS flag in TSFR0 is set to 1 and the slave CPU must analyze the command After command analysis if an OUT...

Page 638: ...Clear Feature command of the host If STALL handshaking is performed because the EPSTL bit is set to 1 the internal bit of the USB function core is also set to a stall state Even if the host clears th...

Page 639: ...P3STL 0 R W Endpoint 4 Stall Sets endpoint 4 in a stall state 0 Endpoint 4 is in an operating state Stall state can be cancelled by the ClearFeature command Clearing condition SCME 1 STALL handshake r...

Page 640: ...of endpoint 2 is performed 1 Endpoint 2 is in a stall state Clearing condition SCME 1 1 is written to EP2STL after EP2STL 0 has been read 1 0 R Reserved This bit is always read as 0 and cannot be mod...

Page 641: ...5 Reset Initializes endpoint 5 FIFO 0 Normal read value 1 A command to reset the endpoint 5 FIFO is issued to the RFU 5 EP4RST 0 R W Endpoint 4 Reset Initializes endpoint 4 FIFO 0 Normal read value 1...

Page 642: ...FO 0 Normal read value 1 FVSR1 is initialized to H 0010 EP1 FIFO size is 16 bytes FVSR1 is initialized to H 0020 EP1 FIFO size is 32 bytes 1 EP0IRST 0 R W Endpoint 0I Reset Initializes endpoint 0I FIF...

Page 643: ...t see section 18 3 16 USB Control Registers 0 and 1 USBCR0 USBCR1 Bit Bit Name Initial Value R W Description 7 to 2 All 0 R Reserved These bits are always read as 0 and cannot be modified 1 RMUPS 0 R...

Page 644: ...to EPIBS0 bits 1 Requests a USBIB interrupt by a TF flag interrupt in USBIFR0 and specifies a TF flag interrupt source endpoint by the EPIBS2 to EPIBS0 bits 6 5 4 EPIBS2 EPIBS1 EPIBS0 0 0 0 R W R W R...

Page 645: ...scription 2 1 0 EPICS2 EPICS1 EPICS0 0 0 0 R W R W R W Interrupt C Endpoint Select 2 to 0 Combined with the TSELC bit selects a USBIC interrupt source 000 Selects no endpoint 001 Selects endpoint 1 01...

Page 646: ...Input Output Analog 1 Digital Selection Selects the USB module data input output method 0 Selects the USDP and USDM pins as USB module data input output 1 Multiplexes the control input output of the...

Page 647: ...ration is stabilized 0 Sets DPLL in operating state 1 Sets DPLL in reset state 0 FSRST 1 R W Function Core Internal State Software Reset Resets the internal state of the USB function core Setting this...

Page 648: ...resistors must be turned ON or OFF by using the general ports 0 Prevents feedthrough current from generating by disconnecting VBUS The USDP and USDM pins are placed in high impedance state 1 VBUS con...

Page 649: ...Differential input P65 XVERDATA Input RCV Data input P64 TXDPLS Output VPO Differential input P63 TXDMNS Output VMO Differential input P62 TXENL Output OE Output enable P61 SUSPEND Output SUSPEND Sus...

Page 650: ...ation and no clock is input to the PLL 100 Setting prohibited 101 PLL stops operation and the USEXCL pin input 48 MHz is directly used instead of PLL output 110 PLL operates using the system clock gen...

Page 651: ...the SetConfiguration and SetInterface command CONFV is initialized to H 00 by a system reset or function software reset see section 18 3 16 USB Control Registers 0 and 1 USBCR0 USBCR1 CONFV Bit Bit N...

Page 652: ...nt 4 is controlled by the USB module and transmit data is transferred from the RFU until the number of transmit data bytes reaches the value specified in EP4PKTSZR EP4PKTSZR is initialized to H 40 by...

Page 653: ...aring the EP5UDTR bit to 0 when there is a space of at least two bytes in the RAM FIFO data in the receive buffer is transferred to the RAM FIFO and the EP5TS bit is set to 1 after transfer completes...

Page 654: ...SCME 0 R W Stall Cancellation Mode Enable Specifies the auto clear function of the EPSTL bit in EPSTLR0 0 Does not specify the auto clear function of the EPSTL bit 1 Specifies the auto clear function...

Page 655: ...stem reset UPRTCR UTESTR0 and UTESTR1 are not initialized in software standby mode UPRTCR Bit Bit Name Initial Value R W Description 7 to 3 All 0 R Reserved These bits are always read as 0 and cannot...

Page 656: ...IN OUT FIFO IN OUT FIFO IN OUT FIFO 1 1 0 IN 8 bytes IN 2048 bytes Maximum OUT 2048 bytes Maximum The USB function core supports a control transfer by endpoint 0 interrupt transfer by endpoints 1 to 3...

Page 657: ...as required Table 18 4 shows the USB function core and slave CPU functions and the registers flags and bits used for interface Table 18 4 USB Function Core and Slave CPU Functions No Function Operati...

Page 658: ...iated if the EPTE bit is set otherwise a NAK handshaking is performed After an IN transaction has been completed transfer normal completion or abnormal completion is determined by the host handshaking...

Page 659: ...age IN token packet NAK STALL handshake packet slave to host Control read transfer Status stage OUT token packet OUT data packet host to slave ACK NAK STALL handshake packet slave to host IN data pack...

Page 660: ...F interrupt occurrence Read TFFR0 and check the EP0OTF interrupt occurrence Complete the USBIA interrupt processing Check if the command decode by the slave CPU is required or not and modify the infor...

Page 661: ...upt occurrence Read TSFR0 and check the EP0OTS interrupt occurrence Check if the command decode by the slave CPU is required by the stored information Complete the USBIA interrupt processing Notes 1 S...

Page 662: ...e CPU Do not modify FVSR0S Note Set the EP0OTC bit of USECSR0 to 1 initialize FVSR0S FVSR0I and FVSR0O clear the EP0ITS and EP0OTS bits of TSFR0 to 0 clear the EP0ITF and EP0OTF bits of TFFR0 to 0 and...

Page 663: ...e FVSR0S FVSR0I and FVSR0O clear the EP0ITS and EP0OTS bits of TSFR0 to 0 clear the EP0ITF and EP0OTF bits of TFFR0 to 0 and clear the EP0STL bit of EPSTLR0 to 0 2 Since a USBIA interrupt is only assi...

Page 664: ...In this case if a USBIB or USBIC interrupt occurs interrupt source determination process is not required Note that TSFR0 must be accessed to clear the flags Receive an OUT token packet Receive an ACK...

Page 665: ...AK to the host CPU Send NAK to the slave CPU Request an USBID interrupt EP2TF 1 Disable data write because the EP2 FIFO is full Restore FVSR2 Initiate the USBID interrupt processing Read USBIFR0 and c...

Page 666: ...CK handshake packet Send ACK to the host Send ACK to the slave CPU Request an USBID interrupt EP5TS 1 Initiate the USBID interrupt processing Read USBIFR0 and check if a TS interrupt occurs or not Rea...

Page 667: ...equest RFU transmission A RAM FIFO full error occurs Initiate the USBID interrupt processing Read USBIFR0 and check if a TF interrupt occurs or not Read TFFR0 and check if an EP5TF interrupt occurs or...

Page 668: ...must be rewound to generate an EP2TF interrupt This EP2TF interrupt must be handled in the same way as when an IN token is received while the FIFO is empty since an EP2TF interrupt caused by a NAK han...

Page 669: ...Request an USBID interrupt EP2TF 1 Initiate the USBID interrupt processing Read USBIFR0 and check if a TF interrupt occurs or not Read TFFR0 and check if an EP2TF interrupt occurs or not Read FVSR2 an...

Page 670: ...ansmit buffer is necessary Receive an IN token packet Send an ACK handshake packet Receive ACK Send ACK to the slave CPU Request a USBID interrupt EP4TS Write data to the EP4 transmission buffer pre r...

Page 671: ...eck if a TF interrupt occurs or not Read TSFR0 and check if an EP2TF interrupt occurs or not Read the RFU pointer write data to EP4 RAM FIFO for the number of bytes which can be written to and modify...

Page 672: ...RSMR If remote wakeup is enabled remote wakeup is performed by setting the DVR bit of DEVRSMR to 1 18 4 6 USB Module Reset and Operation Stop Modes The USB module can be placed in a reset state or ope...

Page 673: ...e after reset cancellation Software Standby Mode Software standby mode is entered if the SLEEP instruction is executed while the SSBY bit of SBYCR is set to 1 In software standby mode the USB module i...

Page 674: ...information of the USB function core are also initialized Therefore initialization by the FSRST or UIFRST bit in USBCR0 should not be performed in the bus reset interrupt processing USB Suspend State...

Page 675: ...e multiplication rate of the PLL circuit can be specified by the PFSEL bit in UPLLCR The 48 MHz clock generated by the PLL circuit can be divided to generate a 24 MHz clock This 24 MHz clock can be us...

Page 676: ...re A total of 65 bytes A1 A2 A5 B1 B2 M4 M5 must be written to EDPR0I in this order Table 18 7 Endpoint Information 1 2 3 4 5 A H 00 H 00 H 11 H 00 H 00 B H 14 H 38 H 10 H 00 H 01 C H 24 H 38 H 10 H 0...

Page 677: ...to 1 by firmware 6 Specify UPLLCR by firmware and wait for USB operating clock PLL stabilization time 3 ms 7 Set the CK48READY bit in USBCR1 to 1 by firmware 8 Clear the UIFRST bit in USBCR0 to 0 by...

Page 678: ...e is connected Clear the FSRST bit of USBCR0 to 0 Externally pull up the USDP pin Read USBIFR0 and check if a BRSTF interrupt occurs or not Set the BRSTF bit of USBIFR0 to 1 Request an USBID interrupt...

Page 679: ...ivation interrupt sources Table 18 8 USB Interrupt Sources When SETICNT of USBMDCR Is 0 Interrupt Source Description DTC Activation Priority USBI0 USBIA An interrupt by SETUP Possible High USBI1 USBIB...

Page 680: ...SEL bit to before DTC activation 2 USB module operation can be enabled or disabled by the SMSTPB1 bit in subchip module stop control register BL SUBMSTPBL In the initial state USB module operation is...

Page 681: ...he MCIF also supports commands extended by the secure multimedia card Secure MultiMediaCard 1 hereafter referred to as Secure MMC Notes 1 MultiMediaCard is a trademark of Infineon Technologies AG Secu...

Page 682: ...DDIR MMC connection signals see table 19 1 TBNCR DTOUTR IOMCR MODER CLKON INTCR0 INTCR1 INTSTR0 INTSTR1 CSTR Internal data bus Bus interface Module data bus RFU interface MMC SPI mode control Data tra...

Page 683: ...re connected to the Data out pin on the MMC side MCCSA ExMCCSA Output Card A selection output pins in SPI mode active low signal These pins are connected to the CS pin on the MMC side MCCSB ExMCCSB Ou...

Page 684: ...r TBCR Transfer block number counter TBNCR Command registers 0 to 5 CMDR0 to CMDR5 Response registers 0 to 16 RSPR0 to RSPR16 Response register D RSPRD Command start register CMDSTRT Operation control...

Page 685: ...ce The command sequence starts from sending a command by setting the START bit in CMDSTRT to 1 and ends when all necessary data transmission reception and response reception has been completed The MMC...

Page 686: ...This bit is set to 1 when the CMD12M command is specified The CMD12M command can be used only in MMC mode Bits TY1 and TY0 should be cleared to B 00 3 TY3 0 R W Specifies stream transfer Bits TY1 and...

Page 687: ...RTY0 should be set to B 011 B 100 or B 101 3 0 R Reserved This bit is always read as 0 and cannot be modified 2 1 0 RTY2 RTY1 RTY0 0 0 0 R W R W R W These bits specify the number of command response b...

Page 688: ...T_CARD R1b 00 1 1 100 CMD9 SEND_CSD R2 R1 00 101 001 CMD10 SEND_CID R2 R1 00 101 001 CMD11M 1 READ_DAT_UNTIL_STOP R1 1 01 1 100 CMD12M 1 STOP_TRANSMISSION R1b 1 00 1 1 100 CMD13 SEND_STATUS R1 R2 00 1...

Page 689: ...mmand index of commands that are available only in MMC mode Similarly S is added to the end of the command index of commands that are available only in SPI mode 2 If there is a difference between the...

Page 690: ...R Reserved These bits are always read as 0 and cannot be modified 3 2 1 0 CS3 CS2 CS1 CS0 0 0 0 0 R W R W R W R W Transfer Data Block Size 0000 1 byte 0001 2 bytes 0010 4 bytes 0011 8 bytes 0100 16 by...

Page 691: ...value H 00 CMDR1 to CMDR4 Command argument of 32 bits Command argument writing Initial value H 00 CMDR5 CRC of 7 bits End bit Automatic calculation for CRC End bit is fixed to 1 Initial value Undefin...

Page 692: ...esponse bytes and valid RSPR register The data response is shifted in from bit 0 in RSPRD and shifted 8 bits only when a command includes write data in SPI mode For other commands the data response is...

Page 693: ...2 5 Bytes in SPI Mode R3 6 Bytes in MMC Mode R1 R1b R3 R4 17 Bytes in MMC Mode R2 RSPR0 1st byte RSPR1 2nd byte RSPR2 3rd byte RSPR3 4th byte RSPR4 5th byte RSPR5 6th byte RSPR6 7th byte RSPR7 8th byt...

Page 694: ...ld not be changed until the command sequence has ended the CWRE flag in CSTR has been reset or a command transmission end interrupt has been generated The command sequences are controlled by the seque...

Page 695: ...is not affected 1 Command sequence is forcibly aborted Byte transfer during transfer is also suspended After command sequence abort the transfer clock output resumes if the transfer clock has been ha...

Page 696: ...eserved The initial value should not be changed The command sequence on the MMC side may be halted according to the status of MMC Table 19 5 shows the MMC states in which the command sequence is halte...

Page 697: ...set to 1 when only one byte of data remains in the transmit data FIFO The receive data FIFO should be read when the FIFO becomes full and the RD_CONTI bit should be set to 1 after three bytes or more...

Page 698: ...en the command sequence has been aborted by setting the CMDOFF bit to 1 after which the DTOUTC stops counting the prescaler output When the command sequence does not end the DTOUTC continues counting...

Page 699: ...full is detected After FIFO full detection this bit is cleared to 0 when resuming to receive read data from the MMC or when the command sequence ends 5 FIFO_EMPTY 0 R FIFO Empty Indicates whether tra...

Page 700: ...execution in progress 1 MMC indicates data busy after command sequence ends 2 DTBUSY_TU R Data Busy Pin Status Monitors level of the MCDAT pin in MMC mode or MCRxD pin in SPI mode This bit is monitore...

Page 701: ...bit as 1 the data response interrupt request is enabled 4 DTIE 0 R W Data Transfer End Interrupt Enable When this bit is set to 1 while the INTRQ1E bit is 1 the data transfer end interrupt request is...

Page 702: ...Enable 0 Disables MCIF0 interrupt to the CPU 1 Enables MCIF0 interrupt to the CPU 4 3 All 0 R Reserved These bits are always read as 0 and cannot be modified 2 CRCERIE 0 R W CRC Error Interrupt Enable...

Page 703: ...EIE 1 in INTCR0 when the FIFO_EMPTY bit in CSTR is set Clearing condition Write 0 after reading FEI 1 6 FFI 0 R W FIFO Full Interrupt Flag 0 No interrupts 1 MCIFI0 interrupt requested Setting conditio...

Page 704: ...TCR0 Clearing condition Write 0 after reading DTI 1 3 CRPI 0 R W Command Response End Interrupt Flag 0 No interrupts 1 MCIFI1 interrupt requested Setting condition When command response reception ends...

Page 705: ...n INTCR0 When the DTBUSY bit in CSTR is cleared Clearing condition Write 0 after reading DBSYI 1 0 BTI 0 R W Multiblock Transfer End Interrupt Flag 0 No interrupts 1 MCIFI1 interrupt requested Setting...

Page 706: ...INTCR1 For the command response CRC should be checked when the RTY4 bit in RSPTYR is enabled Clearing condition Write 0 after reading CRCERI 1 1 DTERI 0 R W Data Timeout Error Interrupt Flag 0 No int...

Page 707: ...aximum of two MMCs are connected to the MCCSA and MCCSB pins 6 CHIPSA 0 R W MMC Selection A B Specifies selection of two MMCs while SPCNUM 1 0 Outputs CS signal from the MCCSA pin and sets the MCCSB p...

Page 708: ...eeded and bits CSEL2 to CSEL0 should be set to B 100 for a 20 Mbps transfer clock according to the limitation of the maximum operating frequency of this LSI At this time bits CSEL2 to CSEL0 should be...

Page 709: ...CSA MCDATDIR and MCCSB MCCMDDIR are enabled disabled by the MMCPE bit in IOMCR When the MMCPE bit is set to 1 the CLKON bit should be cleared to 0 so that the transfer clock is applied after the other...

Page 710: ...d MMC 19 5 1 Operation of Broadcast Commands The CMD0 CMD1 CMD2M and CMD4M are broadcast commands The command sequence assigning relative addresses to individual MMCs consists of these commands and th...

Page 711: ...nsmission reception can be executed for the MMC in the transfer state CMD15M sets the addressed MMC to the inactive state CMD55 sets the addressed MMC to the application original extension command acc...

Page 712: ...ted Command transmission ended Command sequence execution period Figure 19 2 Example of Command Sequence for Commands that Do Not Require Command Response CMDI interrupt detected Set command data to C...

Page 713: ...the command sequence for commands without data transfer Figure 19 6 shows the operational flow for commands without data transfer Settings needed to issue a command are made The START bit in CMDSTRT i...

Page 714: ...R0 CSTR CWRE CMDI CRPI DBSYI BUSY REQ DTBUSY DTBUSY_TU Command output 48 bits No busy state Command response reception Command transmission period Command transmission started Response reception compl...

Page 715: ...RPI DBSYI BUSY REQ DTBUSY DTBUSY_TU Command output 48 bits Busy state Command response reception Command transmission period Command transmission started Response reception completed Busy state comple...

Page 716: ...et command data to CMDR0 to CMDR4 Set command type to CMDTYR Set command response type to RSPTYR Set the START bit in CMDSTRT to 1 Yes Yes Yes Busy Not Busy No No No Command sequence start Command seq...

Page 717: ...uence is then continued Figures 19 7 to 19 10 show examples of the command sequence for commands with read data Figure 19 11 shows the operational flow for commands with read data Settings needed to i...

Page 718: ...MCDAT CMDSTRT START INTSTR0 CSTR CWRE RD_CONTI CMDOFF CMDI CRPI DTI FFI BUSY REQ FIFO_FULL Command Read data Command response Command transmission started Single block read command execution sequence...

Page 719: ...FIFO_FULL Command Read data Read data Command response Block data reception suspended Transfer clock transmission halted Transfer clock transmission resumed Block data reception resumed Command transm...

Page 720: ...BUSY REQ FIFO_FULL Command Read data Read data Command response Command Command response Transfer clock transmission halted Command transmission started Multiblock read command execution sequence Mul...

Page 721: ...ead data Read data Command response Command Command response Data reception suspended Writing data to FIFO Data reception resumed Transfer clock transmission halted Transfer clock transmission resumed...

Page 722: ...he RD_CONTI bit to 1 Set the CMDOFF bit to 1 Execute CMD12M Command sequence end Set the CMDOFF bit to 1 Execute CMD12M Command sequence abnormal end Is FFI interrupt detected Is block data read compl...

Page 723: ...sequence for commands with write data Figure 19 16 shows the operational flow for commands with write data Settings needed to issue a command are made Write data is set to the transmit data FIFO The S...

Page 724: ...the DTBUSY flag in CSTR or by the data busy end interrupt DBSYI MCCLK MCCMD CMD24 WRITE_SINGLE_BLOCK MCDAT CMDSTRT START INTSTR0 CSTR CWRE DATAEN CMDOFF CMDI CRPI DTI DRPI FEI DBSYI BUSY FIFO_EMPTY DT...

Page 725: ...E_SINGLE_BLOCK FEI DBSYI DTI CRPI CMDOFF DA TA EN OPCR Transfer clock transmission halted Transfer clock transmission resumed Command transmission started CMDI Write data Write data Busy Block data tr...

Page 726: ...I FEI DBSYI BUSY FIFO_EMPTY DTBUSY REQ DTBUSY_TU Command Write data Multibreak write command sequence Block data transmission started Next block data transmission started Block data reception end Stat...

Page 727: ...esponse Command Command response Busy Data transmission suspended Reading data from FIFO Data transmission suspended Transfer clock transmission halted Transfer clock transmission resumed Transfer clo...

Page 728: ...OFF bit to 1 Execute CMD12M Command sequence end Set the CMDOFF bit to 1 Execute CMD12M Command sequence abnormal end Is FFI interrupt detected Is block data write completed Write data to FIFO Is DTER...

Page 729: ...emory write erase the MMC displays the data busy state Figures 19 17 and 19 18 show examples of the command sequence for commands without data transfer Figure 19 19 shows the operational flow for comm...

Page 730: ...mmand response reception No busy state Response reception ended Command transmission started Command transmission period Command sequence execution period MCCLK MCTxD MCRxD MCCSA CWRE BUSY DTBUSY_TU D...

Page 731: ...on Busy state Command response completed Response reception ended Command transmission started Command transmission period Command sequence execution period MCCLK MCTxD MCRxD MCCSA CWRE BUSY DTBUSY_TU...

Page 732: ...ommand data to CMDR0 to CMDR4 Set command type to CMDTYR Set command response type to RSPTYR Set the START bit in CMDSTRT to 1 Yes Yes Yes Busy Not Busy No No No Command sequence start Command sequenc...

Page 733: ...shows the operational flow for commands with read data Settings needed to issue a command are made The START bit in CMDSTRT is set to 1 to start command transmission The CS signal goes low select Com...

Page 734: ...DRD MCCSA CWRE BUSY FIFO_FULL REQ CSTR CMDSTRT START IINTSTR0 Command Command response Read data Command transmission started Single block read command execution sequence CMD17 READ_SINGLE_BLOCK BTI F...

Page 735: ...ponse Read data Single block read command execution sequence CMD17 READ_SINGLE_BLOCK BTI FFI DTI CRPI CMDOFF RD_CONTI OPCR Read data Transfer clock transmission halted Block data reception suspended B...

Page 736: ...ter Response status Is DTI interrupt detected Command sequence end Command sequence abnormal end Is FFI interrupt detected Does block data read end Read data from FIFO Is DTERI or CRCERI interrupt det...

Page 737: ...eeded to issue a command are made Write data is set to the transmit data FIFO The START bit in CMDSTRT is set to 1 to start command transmission The CS signal goes low select Command transmission comp...

Page 738: ...O_EMPTY REQ CSTR CMDSTRT START IINTSTR0 FFI DTI CRPI CMDOFF DATAEN OPCR CMDI Command Command response Write data Data response Busy CMD24 WRITE_SINGLE_BLOCK Command transmission started Single block w...

Page 739: ...MD24 WRITE_SINGLE_BLOCK Transfer clock transmission halted Transfer clock transmission resumed Write data Write data Data response Busy Block data transmission resumed Block data transmission suspende...

Page 740: ...errupt detected Command sequence end Command sequence abnormal end Is FFI interrupt detected Does block data write end Write data to FIFO Is CTERI or CRCERI interrupt detected Set the DATAEN bit to 1...

Page 741: ...FI Possible Data response DPRI Not possible Data transfer end DTI Not possible Command response end CRPI Not possible Command transmission end CMDI Not possible Data busy end DBSYI Not possible MMCIB...

Page 742: ...Section 19 Multimedia Card Interface MCIF Rev 3 00 Jan 25 2006 page 688 of 872 REJ09B0286 0300...

Page 743: ...Rev 3 00 Jan 25 2006 page 689 of 872 REJ09B0286 0300 Section 20 Encryption Operation Circuit DES and GF This section will be made available on conclusion of a nondisclosure agreement For details conta...

Page 744: ...Section 20 Encryption Operation Circuit DES and GF Rev 3 00 Jan 25 2006 page 690 of 872 REJ09B0286 0300...

Page 745: ...load capacitance is 20 pF Output voltage 0 V to AVref D A output retaining function in software standby mode Module data bus Internal data bus AVref AVCC DA1 DA0 AVSS 8 bit D A Control circuit D A D R...

Page 746: ...analog output Analog output pin 1 DA1 Output Channel 1 analog output Reference power supply pin AVref Input Analog block reference voltage 21 3 Register Descriptions The D A converter has the followin...

Page 747: ...t is cleared to 0 D A conversion for channels 0 and 1 are controlled individually When the DAE bit is set to 1 D A conversion for channels 0 and 1 are controlled as one Conversion result output is con...

Page 748: ...CONV conversion results are output from the analog output pin DA0 The conversion results are output continuously until DADR0 is modified or the DAOE0 bit is cleared to 0 The output value is calculated...

Page 749: ...ower supply current is equal to as during D A conversion If the analog power supply current needs to be reduced in software standby mode clear the DAOE1 DAOE0 and DAE bits all to 0 to disable D A outp...

Page 750: ...Section 21 D A Converter Rev 3 00 Jan 25 2006 page 696 of 872 REJ09B0286 0300...

Page 751: ...can be specified using the reference power supply voltage pin AVref as an analog reference voltage Conversion time Max 5 36 s per channel at 25 MHz operation Two kinds of operating modes Single mode...

Page 752: ...D D R D A D D R C A D D R B A D D R A Successive approximations register AN2 AN3 AN4 AN5 Legend ADCR A D control register ADCSR A D control status register ADDRA A D data register A ADDRB A D data re...

Page 753: ...in Name Symbol I O Function Analog power supply pin AVCC Input Analog block power supply Analog ground pin AVSS Input Analog block ground and reference voltage Reference power supply pin AVref Input A...

Page 754: ...registers which store a conversion result for each channel are shown in table 22 2 The converted 10 bit data is stored to bits 15 to 6 The lower 6 bit data is always read as 0 The data bus between th...

Page 755: ...and ADDR is read 6 ADIE 0 R W A D Interrupt Enable Enables ADI interrupt by ADF when this bit is set to 1 5 ADST 0 R W A D Start Setting this bit to 1 starts A D conversion In single mode this bit is...

Page 756: ...N7 Note Only 0 can be written for clearing the flag 22 3 3 A D Control Register ADCR ADCR enables A D conversion started by an external trigger signal Bit Bit Name Initial Value R W Description 7 6 TR...

Page 757: ...Comparator Scan Enable Enables or disables the DTC comparator scan function 0 Disables DTC comparator scan function 1 Enables DTC comparator scan function 3 KBADE 0 R W Keyboard A D Enable Sets analo...

Page 758: ...DAR 23 to 0 Optional RAM address Lower four bits should be 0 Conversion results of CIN0 to CIN7 are written to eight words leading from this address CRAH 7 to 0 H FF CRAL 7 to 0 H FF DTCERA 3 DTCEA3...

Page 759: ...h 10 bit resolution It has two operating modes single mode and scan mode When changing the operating mode or analog input channel to prevent incorrect operation first clear the ADST bit to 0 in ADCSR...

Page 760: ...he first channel in the group starts again 4 The ADST bit is not automatically cleared to 0 so steps 2 to 3 are repeated as long as the ADST bit remains set to 1 When the ADST bit is cleared to 0 A D...

Page 761: ...ess tD A D conversion start delay tSPL Input sampling time tCONV A D conversion time Figure 22 2 A D Conversion Timing Table 22 4 A D Conversion Time Single Mode CKS 0 CKS 1 Item Symbol min typ max mi...

Page 762: ...me as when the ADST bit has been set to 1 by software Figure 22 3 shows the timing ADTRG Internal trigger signal ADST A D conversion Figure 22 3 External Trigger Input Timing 22 6 Interrupt Source The...

Page 763: ...inimum voltage value B 00_0000_0000 H 000 to B 00_0000_0001 H 001 see figure 22 5 Full scale error The deviation of the analog input voltage value from the ideal A D conversion characteristic when the...

Page 764: ...Quantization error Digital output Ideal A D conversion characteristic Analog input voltage Figure 22 4 A D Conversion Accuracy Definitions FS Offset error Nonlinearity error Actual A D conversion char...

Page 765: ...k and the signal source impedance is ignored However since a low pass filter effect is obtained in this case it may not be possible to follow an analog signal with a large differential coefficient e...

Page 766: ...n DrVCC DrVSS is shared with the analog power supply pin AVCC AVSS 22 8 4 Notes on Board Design In board design digital circuitry and analog circuitry should be as mutually isolated as possible and la...

Page 767: ...of the sample and hold circuit in the A D converter exceeds the current input via the input impedance Rin an error will arise in the analog input pin voltage Careful consideration is therefore require...

Page 768: ...Section 22 A D Converter Rev 3 00 Jan 25 2006 page 714 of 872 REJ09B0286 0300...

Page 769: ...static RAM The RAM is connected to the CPU by a 16 bit data bus enabling one state access by the CPU to both byte data and word data The on chip RAM can be enabled or disabled by means of the RAME bit...

Page 770: ...Section 23 RAM Rev 3 00 Jan 25 2006 page 716 of 872 REJ09B0286 0300...

Page 771: ...ing one block takes 100 ms typ Reprogramming capability The flash memory can be reprogrammed up to 100 times Two flash memory on board programming modes Boot mode User program mode On board programmin...

Page 772: ...ter 2 Module bus Figure 24 1 Block Diagram of Flash Memory 24 2 Mode Transition Diagrams When the mode pins are set in the reset state and a reset start is executed this LSI enters an operating mode a...

Page 773: ...n user mode and user program mode when the CPU is not accessing the flash memory 1 FEW 1 MD2 MD1 MD0 0 2 FEW 1 MD2 1 MD1 MD0 0 P92 0 P91 P90 1 Figure 24 2 Flash Memory State Transitions Table 24 1 Dif...

Page 774: ...how to write over an old version application program or data in the flash memory The user should prepare the programming control program and new application program beforehand in the host 2 SCI commun...

Page 775: ...rogram Transfer program 1 Initial state 1 The program that will transfer the programming erase control program from flash memory to on chip RAM should be written into the flash memory by the user befo...

Page 776: ...E07F H 00EFFF H 00F07F H 00FFFF H 01007F Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 byt...

Page 777: ...ss FLMCR1 FLMCR2 EBR1 or EBR2 the FLSHE bit in the serial timer control register STCR should be set to 1 For details on the serial timer control register see section 3 2 3 Serial Timer Control Registe...

Page 778: ...cannot be set Do not clear these bits and SWE to 0 simultaneously 5 4 All 0 R Reserved These bits are always read as 0 and cannot be modified 3 EV 0 R W Erase Verify When this bit is set to 1 while SW...

Page 779: ...or Protection 6 to 2 All 0 R W Reserved The initial value should not be changed 1 ESU 0 R W Erase Setup When this bit is set to 1 while SWE 1 the flash memory transits to the erase setup state When it...

Page 780: ...Name Initial Value R W Description 7 EB7 0 R W When this bit is set to 1 4 kbytes of EB7 H 00E000 to H 00EFFF are to be erased 6 EB6 0 R W When this bit is set to 1 4 kbytes of EB6 H 00D000 to H 00DF...

Page 781: ...ing Mode Mode MD2 MD2 MD2 MD2 MD1 MD0 EXPE On Chip ROM Mode 2 Advanced Single chip mode 1 1 0 0 Advanced Extended mode with on chip ROM 1 1 0 1 Enabled 256 kbytes Mode 3 Normal Single chip mode 1 1 1...

Page 782: ...to measure the low level period 4 After matching the bit rates this LSI transmits one H 00 byte to the host to indicate the end of bit rate adjustment The host should confirm that this adjustment end...

Page 783: ...high during reset operating modes are switched and the state of ports that are also used for address output and bus control output signals AS RD and HWR are changed 2 Therefore set these pins carefull...

Page 784: ...ers it to RAM repeated for N times High order byte and low order byte Echoback Echoback H XX Transmits number of bytes N of programming control program to be transferred as 2 byte data low order byte...

Page 785: ...ote that the boot program area in the RAM retains the boot program after branching to the programming control program ID code area Programming control program area 6136 bytes Reserved area 2048 bytes...

Page 786: ...cordance with the description in section 24 8 Flash Memory Programming Erasing Yes No Program erase Reset start Branch to flash memory application program Transfer user program erase control program t...

Page 787: ...data storage areas in RAM a 128 byte programming data area a 128 byte reprogramming data area and a 128 byte additional programming data area Perform reprogramming data computation and additional pro...

Page 788: ...nd reprogram data area Apply write pulse Additional programming z3 s 128 byte data verification completed Successively write 128 byte data from additional programming data area in RAM to flash memory...

Page 789: ...ck must be erased in turn 3 The time during which the E bit is set to 1 is the flash memory erase time 4 The watchdog timer WDT is set to prevent overprogramming due to program runaway etc An overflow...

Page 790: ...FLMCR1 Wait s Clear EV bit in FLMCR1 Clear SWE bit in FLMCR1 Disable WDT End of erasing 1 Verify data all 1 Last address of block All erase blocks erased Erase failure Clear SWE bit in FLMCR1 n N NG...

Page 791: ...ocks by clearing the SWE bit in FLMCR1 to 0 When software protection is in effect setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode By setting the erase block...

Page 792: ...ormal vector reading cannot be performed in interrupt exception handling during programming erasing 2 3 If an interrupt occurs during boot program execution the normal boot mode sequence cannot be exe...

Page 793: ...re and other factors 3 Perform flash memory programming erasing in accordance with the recommended algorithm In the recommended algorithm flash memory programming erasing can be performed without subj...

Page 794: ...r than that of the external interrupt vector table To write data or programs to the flash memory data or programs must be allocated to addresses higher than that of the external interrupt vector table...

Page 795: ...Port and Boundary Scan Architecture and a pin compatible serial interface The H UDI performs serial transfer by means of external signal control 25 1 Features The H UDI has the following features con...

Page 796: ...e 742 of 872 REJ09B0286 0300 TAP controller ETCK ETMS ETRST ETDO Mux SDIR Decoder SDBPR SDIR SDBPR SDBSR SDIDR Instruction register Bypass register Boundary scan register ID code register ETDI SDIDR S...

Page 797: ...elect input Sampled on the rise of the ETCK pin The ETMS pin controls the internal state of the TAP controller If there is no input the ETMS pin is fixed to 1 by an internal pull up Test data input ET...

Page 798: ...mode The ID code register SDIDR is a 32 bit register a fixed code can be output via the ETDO pin in IDCODE mode All registers cannot be accessed directly by the CPU Table 25 2 shows the kinds of seri...

Page 799: ...1101 Setting prohibited 1110 IDCODE mode Initial value 1111 BYPASS mode 27 to 14 All 0 R Reserved These bits are always read as 0 and cannot be modified 13 1 R Reserved This bit is always read as 1 an...

Page 800: ...is connected between the ETDI and ETDO pins 25 3 3 Boundary Scan Register SDBSR SDBSR is a shift register provided on the PAD for controlling the I O terminals of this LSI Using EXTEST mode or SAMPLE...

Page 801: ...No from ETDI 4 MD2 Input 214 5 MD1 Input 213 6 MD0 Input 212 7 NMI Input 211 13 P51 Input Enable Output 210 209 208 14 P50 Input Enable Output 207 206 205 16 P97 Input Enable Output 204 203 202 17 P9...

Page 802: ...185 184 23 P92 Input Enable Output 183 182 181 24 P91 Input Enable Output 180 179 178 25 P90 Input Enable Output 177 176 175 26 P60 Input Enable Output 174 173 172 27 P61 Input Enable Output 171 170 1...

Page 803: ...7 Input Enable Output 153 152 151 38 USDP Input Enable Output 150 149 148 39 USDM Input Enable Output 147 146 145 40 P72 Input 144 41 P73 Input 143 42 P74 Input 142 43 P75 Input 141 44 P76 Input 140 4...

Page 804: ...125 124 52 P41 Input Enable Output 123 122 121 53 P42 Input Enable Output 120 119 118 54 P43 Input Enable Output 117 116 115 55 P44 Input Enable Output 114 113 112 56 P45 Input Enable Output 111 110...

Page 805: ...ble Output 96 95 94 63 P24 Input Enable Output 93 92 91 64 P23 Input Enable Output 90 89 88 65 P22 Input Enable Output 87 86 85 66 P21 Input Enable Output 84 83 82 67 P20 Input Enable Output 81 80 79...

Page 806: ...ble Output 66 65 64 77 P12 Input Enable Output 63 62 61 78 P11 Input Enable Output 60 59 58 79 P10 Input Enable Output 57 56 55 80 P87 Input Enable Output 54 53 52 81 P86 Input Enable Output 51 50 49...

Page 807: ...able Output 36 35 34 87 P35 Input Enable Output 33 32 31 88 P36 Input Enable Output 30 29 28 89 P37 Input Enable Output 27 26 25 90 P85 Input Enable Output 24 23 22 91 P84 Input Enable Output 21 20 19...

Page 808: ...esponding pin is driven with the output value If either the enable signal for the USDP pin or that for the USDM pin is driven high both pins are driven by the output values 25 3 4 ID Code Register SDI...

Page 809: ...gic Reset Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Select DR Scan Run Test Idle 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 0 Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR Sel...

Page 810: ...ts are not affected by execution of this instruction In a SAMPLE operation a snapshot of a value to be transferred from an input pin to the internal circuitry or a value to be transferred from the int...

Page 811: ...ction is enabled the state of the boundary scan register maintains the previous state regardless of the state of the TAP controller A bypass register is connected between the ETDI and ETDO pins The re...

Page 812: ...pin of the board tester from being affected by the LSI system reset circuits must be separated Figure 25 3 shows a design example of the reset signal circuit wherein no reset signal interference occur...

Page 813: ...pled while its open drain function is enabled and its corresponding output scan register is 1 0 can be detected at the corresponding enable scan register ETDI SDIR SDIR ETDO Shift register Shift regis...

Page 814: ...DR is captured into the shift register in Capture DR in IDCODE mode and bits 0 to 31 of SDIDR are output in that order from the ETDO pin in Shift DR Data input from the ETDI pin is written to any regi...

Page 815: ...ion circuit and USB operating clock select circuit WDT_1 count clock System clock To pin Internal clock To peripheral modules Bus master clock To CPU and DTC EXTAL PLL circuit XTAL EXCL USEXCL 2 to 32...

Page 816: ...onnecting a crystal resonator An appropriate damping resistance Rd given in table 26 1 should be used An AT cut parallel resonance crystal resonator should be used Figure 26 3 shows the equivalent cir...

Page 817: ...citance should be 10 pF or less To input an inverted clock to the XTAL pin the external clock should be set to high in standby mode subactive mode subsleep mode and watch mode External clock input con...

Page 818: ...0 4 0 6 0 4 0 6 tcyc Figure 29 4 tEXH tEXL tEXr tEXf VCC 0 5 EXTAL Figure 26 5 External Clock Input Timing The oscillator and duty correction circuit have a function to adjust the waveform of the ext...

Page 819: ...00 s Figure 26 6 Note tDEXT includes a RES pulse width tRESW tDEXT RES Internal and external EXTAL STBY VCC 2 7 V VIH Note The external clock output stabilization delay time tDEXT includes a RES pulse...

Page 820: ...input circuit controls subclock input from the EXCL pin To use the subclock a 32 768 kHz external clock should be input from the EXCL pin At this time the P96DDR bit in P9DDR should be cleared to 0 a...

Page 821: ...are standby mode A clock generated by an oscillator to which the EXTAL and XTAL pins are input is selected as a system clock when returning from the reset state or hardware standby mode A subclock inp...

Page 822: ...tor are closely related to the board design by the user use the example of resonator connection in this document for only reference be sure to use an resonator that has been sufficiently evaluated by...

Page 823: ...Generator Rev 3 00 Jan 25 2006 page 769 of 872 REJ09B0286 0300 26 9 3 Processing for X1 and X2 Pins The X1 and X2 pins should be left open as shown in figure 26 9 X1 X2 Open Open Figure 26 9 Processi...

Page 824: ...Section 26 Clock Pulse Generator Rev 3 00 Jan 25 2006 page 770 of 872 REJ09B0286 0300...

Page 825: ...e mode The CPU operates based on the subclock and on chip peripheral modules other than TMR_0 TMR_1 WDT_0 and WDT_1 stop operating Sleep mode The CPU stops but on chip peripheral modules continue oper...

Page 826: ...register L MSTPCRL Sub chip module stop control register BH SUBMSTPBH Sub chip module stop control register BL SUBMSTPBL 27 1 1 Standby Control Register SBYCR SBYCR controls power down modes Bit Bit...

Page 827: ...han the CPU in medium speed mode 0 All bus masters operate based on the medium speed clock 1 The DTC RFU operates based on the system clock The operating clock is changed when a DTC RFU transfer is re...

Page 828: ...ecification Note This setting cannot be made in the flash memory version of this LSI 27 1 2 Low Power Control Register LPWRCR LPWRCR controls power down modes Bit Bit Name Initial Value R W Descriptio...

Page 829: ...cancelled 0 Shifts to high speed mode 1 Shifts to subactive mode 5 NESEL 0 R W Noise Elimination Sampling Frequency Select Selects the frequency by which the subclock SUB input from the EXCL pin is sa...

Page 830: ...s not switched and operation shifts to sleep mode 0 Enters software standby mode or watch mode and switches to the system clock source specified by the PLCKS bit 1 Directly switches to the system cloc...

Page 831: ...ler DTC 5 MSTP13 1 R W 16 bit free running timer FRT 4 MSTP12 1 R W 8 bit timers TMR_0 TMR_1 3 MSTP11 1 R W 8 bit PWM timer PWM 14 bit PWM timer PWMX 2 MSTP10 1 R W D A converter 1 MSTP9 1 R W A D con...

Page 832: ...PB5 1 R W 4 SMSTPB4 1 R W 3 SMSTPB3 1 R W 2 SMSTPB2 1 R W 1 SMSTPB1 1 R W Universal serial bus interface USB 0 SMSTPB0 1 R W Note Do not clear this bit to 0 27 2 Mode Transitions and LSI States Figure...

Page 833: ...ON 1 SSBY 1 PSS 1 DTON 0 RES pin High Transition after exception processing Power down mode Reset state High speed mode main clock Medium speed mode main clock Sub active mode sub clock Sub sleep mode...

Page 834: ...g Function ing Function ing Halted retained Halted retained Halted retained Halted retained Halted retained Halted reset WDT_1 Function ing Function ing Function ing Subclock operation WDT_0 Function...

Page 835: ...with respect to the bus master operating clock For example if 4 is selected as the operating clock on chip memory is accessed in 4 states and internal I O registers in 8 states By clearing all of bit...

Page 836: ...nd interrupt exception handling starts Sleep mode is not exited if the interrupt is disabled or interrupts other than NMI are masked by the CPU Setting the RES pin level low cancels sleep mode and sel...

Page 837: ...o 0 or if the interrupt has been masked by the CPU In the case of a KIN9 to KIN0 or WUE15 to WUE8 interrupt software standby mode is not exited if input is disabled or if the interrupt has been masked...

Page 838: ...g as the prescribed voltage is supplied on chip RAM data is retained The I O ports are set to the high impedance state In order to retain on chip RAM data the RAME bit in SYSCR should be cleared to 0...

Page 839: ...ained and the I O ports retain their values before transition as long as the prescribed voltage is supplied Watch mode is exited by an interrupt WOVI1 NMI IRQ15 to IRQ0 KIN9 to KIN0 or WUE15 to WUE8 R...

Page 840: ...ule registers and on chip RAM data are retained and the I O ports retain their values before transition as long as the prescribed voltage is supplied Subsleep mode is exited by an interrupt interrupts...

Page 841: ...o watch mode When the SLEEP instruction is executed with the SSBY bit in SBYCR cleared to 0 the LSON bit in LPWRCR set to 1 and the PSS bit in TCSR WDT_1 set to 1 a transition is made to subsleep mode...

Page 842: ...t to 11 and the PSS bit in TSCR WDT_1 set to 1 To make a direct transition to high speed mode after the time set in the STS2 to STS0 bits in SBYCR has elapsed execute the SLEEP instruction in subactiv...

Page 843: ...s not reduced by the amount of current to support the high level output 27 12 2 Current Consumption when Waiting for Oscillation Stabilization The current consumption increases during oscillation stab...

Page 844: ...Section 27 Power Down Modes Rev 3 00 Jan 25 2006 page 790 of 872 REJ09B0286 0300...

Page 845: ...by in the bit name column The bit number in the bit name column indicates that the whole register is allocated as a counter or for holding data 16 bit registers are indicated from the bit on the MSB s...

Page 846: ...E MCIF 8 3 Interrupt status register 1 INTSTR1 8 H FBCF MCIF 8 3 Transfer clock control register CLKON 8 H FBD0 MCIF 8 3 Command timeout control register CTOCR 8 H FBD1 MCIF 8 3 Pin mode control regis...

Page 847: ...D81 USB 8 3 Endpoint data register 0S EPDR0S 8 H FDAD USB 8 3 FIFO valid size register 0SH FVSR0SH 8 H FDAE USB 8 3 FIFO valid size register 0SL FVSR0SL 8 H FDAF USB 8 3 USB interrupt enable register...

Page 848: ...DF0 USB 8 3 USB interrupt enable register 0 USBIER0 8 H FDF1 USB 8 3 USB interrupt flag register 0 USBIFR0 8 H FDF2 USB 8 3 Transfer normal completion interrupt flag register 0 TSFR0 8 H FDF3 USB 8 3...

Page 849: ...us register B DTSTRB 8 H FEAB RFU 8 3 Data transfer control register D DTCRD 8 H FEAC RFU 8 3 Data transfer interrupt enable register DTIER 8 H FEAD RFU 8 3 Data transfer register select register DTRS...

Page 850: ...16 2 Serial enhanced mode register_0 SEMR_0 8 H FED0 SCI_0 8 2 Serial RFU enable register 0 SCIDTER_0 8 H FED1 SCI_0 8 2 Serial enhanced mode register_2 SEMR_2 8 H FED2 SCI_2 8 2 Serial RFU enable reg...

Page 851: ...ol register 16H ISCR16H 8 H FEFA INT 8 2 IRQ sense control register 16L ISCR16L 8 H FEFB INT 8 2 IRQ sense port select register 16 ISSR16 8 H FEFC INT 8 2 IRQ sense port select register ISSR 8 H FEFD...

Page 852: ...address register_1 SAR_1 8 H FF8F IIC_1 8 2 Timer interrupt enable register TIER 8 H FF90 FRT 8 2 Timer control status register TCSR 8 H FF91 FRT 8 2 Free running counter H FRCH 8 H FF92 FRT 8 2 Free...

Page 853: ...2 BRR_2 8 H FFA1 SCI_2 8 2 Serial control register_2 SCR_2 8 H FFA2 SCI_2 8 2 Transmit data register_2 TDR_2 8 H FFA3 SCI_2 8 2 Serial status register_2 SSR_2 8 H FFA4 SCI_2 8 2 Receive data register_...

Page 854: ...5 data register P5DR 8 H FFBA PORT 8 2 Port 6 data register P6DR 8 H FFBB PORT 8 2 Port 8 data direction register P8DDR 8 H FFBD PORT 8 2 Port 7 input data register P7PIN 8 H FFBE PORT 8 2 Port 8 dat...

Page 855: ...erial mode register_0 SMR_0 8 H FFD8 SCI_0 8 2 I2 C bus control register_0 ICCR_0 8 H FFD8 IIC_0 8 2 Bit rate register_0 BRR_0 8 H FFD9 SCI_0 8 2 I2 C bus status register_0 ICSR_0 8 H FFD9 IIC_0 8 2 S...

Page 856: ...counter_1 TCNT_1 8 H FFEA write WDT_1 8 2 Timer counter_1 TCNT_1 8 H FFEB read WDT_1 8 2 Keyboard matrix interrupt mask register 6 KMIMR6 8 H FFF1 INT 8 2 Port 6 pull up MOS control register KMPCR6 8...

Page 857: ...SR 8 H FFF5 TMR_Y 16 2 Time constant register A_X TCORA_X 8 H FFF6 TMR_X 16 2 Time constant register B_X TCORB_X 8 H FFF7 TMR_X 16 2 D A data register 0 DADR0 8 H FFF8 D A converter 8 2 D A data regis...

Page 858: ...INTCR0 FEIE FFIE DRPIE DTIE CRPIE CMDIE DBSYIE BTIE INTCR1 INTRQ2E INTRQ1E INTRQ0E CRCERIE DTERIE CTERIE INTSTR0 FEI FFI DRPI DTI CRPI CMDI DBSYI BTI INTSTR1 CRCERI DTERI CTERI CLKON CLKON CSEL2 CSEL1...

Page 859: ...Bit 11 Bit 10 Bit 9 Bit 8 RSPR16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PSPRD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DTOUTRH DTOUT15 DTOUT14 DTOUT13 DTOUT12 DTOUT11 DTOUT10 DTOUT9 D...

Page 860: ...TS EP0ITS EP0OTS TFFR0 EP5TF EP4TF EP3TF EP2TF EP1TF EP0ITF EP0OTF USBCSR0 EP0STOP EPIVLD EP0OTC EPSTLR0 EP5STL EP4STL EP3STL EP2STL EP1STL EP0STL EPDIR0 EP5DIR EP4DIR EP3DIR EP2DIR EP1DIR EPRSTR0 EP5...

Page 861: ...I MSTX TRSX WAITX ACKXE ICSRB_0 CREQ CERR STOP ABRT ALST DERR TOVR NACK ICSRC_0 MTREQ MRREQ STREQ SRREQ MASX TDRE SDRF RDRF ICDRX_0 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 ICCMD_0 Bit 7 Bit 6...

Page 862: ...CA IRQ4SCB IRQ4SCA ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA INT DTCERA IRQ0 IRQ1 IRQ2 IRQ3 ADI ICIA ICIB OCIA DTCERB OCIB IICM0 IICR0 IICT0 CMIA0 CMIB0 CMIA1 DTCERC CMIB1...

Page 863: ...R_1 ICE IEIC MST TRS ACKE BBSY IRIC SCP IIC_1 BRR_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCI_1 ICSR_1 ESTP STOP IRTR AASX AL AAS ADZ ACKB IIC_1 SCR_1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDR_1...

Page 864: ...Bit 0 ICRCH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 OCRDMH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 ICRCL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OCRDML Bit 7 Bit 6...

Page 865: ...R P20DR P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR P4DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR P3DR P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR P4DR P47DR P46D...

Page 866: ...R_0 TMR_1 PWOERB OE15 OE14 OE13 OE12 OE11 OE10 OE9 OE8 PWOERA OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0 PWDPRB OS15 OS14 OS13 OS12 OS11 OS10 OS9 OS8 PWDPRA OS7 OS6 OS5 OS4 OS3 OS2 OS1 OS0 PWSL PWCKE PWCKS RS3 R...

Page 867: ...CR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR PORT KMIMRA KMIM9 KMIM8 WUEMR3 WUEM15 WUEM14 WUEM13 WUEM12 WUEM11 WUEM10 WUEM9 WUEM8 INT TCR_X CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TCR_Y CMIEB CMIE...

Page 868: ...Bit 3 Bit 2 Bit 1 Bit 0 DACR DAOE1 DAOE0 DAE D A converter TCONRI SIMOD1 SIMOD0 SCONE ICST HFINV VFINV HIINV VIINV TCONRO HOE VOE CLOE CBOE HOINV VOINV CLOINV CBOINV TCONRS TMRX Y ISGENE HOMOD1 HOMOD0...

Page 869: ...ized IOMCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized TBCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized MODER Initialize...

Page 870: ...nitialized Initialized Initialized EP4PKTSZR Initialized 1 Initialized EPDR0S Initialized 1 Initialized FVSR0SH Initialized 1 Initialized FVSR0SL Initialized 1 Initialized USBIER1 Initialized 1 Initia...

Page 871: ...nitialized SUBMSTPBH Initialized Initialized SUBMSTPBL Initialized Initialized SYSTEM FSTR0 Initialized Initialized FSTR1 Initialized Initialized FSTR2 Initialized Initialized FSTR3 Initialized Initia...

Page 872: ...2 Initialized Initialized SCI_2 CRCCR Initialized Initialized CRCDIR Initialized Initialized CRCDORH Initialized Initialized CRCDORL Initialized Initialized CRC KBCOMP Initialized Initialized A D conv...

Page 873: ...ed 2 3 Initialized 2 Initialized 2 Initialized 2 Initialized 2 Initialized EBR1 Initialized 3 Initialized Initialized Initialized Initialized Initialized EBR2 Initialized 3 Initialized Initialized Ini...

Page 874: ...CR Initialized Initialized Initialized Initialized Initialized Initialized Initialized DADRAH Initialized Initialized Initialized Initialized Initialized Initialized Initialized DADRAL Initialized Ini...

Page 875: ...d P4DDR Initialized Initialized P3DR Initialized Initialized P4DR Initialized Initialized P5DDR Initialized Initialized P6DDR Initialized Initialized PORT P5DR Initialized Initialized P6DR Initialized...

Page 876: ...ialized Initialized SCMR_0 Initialized Initialized SCI_0 ICDR_0 Initialized Initialized SARX_0 Initialized Initialized ICMR_0 Initialized Initialized SAR_0 Initialized Initialized IIC_0 ADDRAH Initial...

Page 877: ...Initialized TMR_Y TMR_X TCORA_Y Initialized Initialized TICRF Initialized Initialized TCORB_Y Initialized Initialized TCNT_X Initialized Initialized TCNT_Y Initialized Initialized TCORC Initialized In...

Page 878: ...Section 28 List of Registers Rev 3 00 Jan 25 2006 page 824 of 872 REJ09B0286 0300...

Page 879: ...elected in port 6 Vin Lower of 0 3 to VCC 0 3 or 0 3 to AVCC 0 3 Input voltage port 7 Vin 0 3 to AVCC 0 3 Reference power supply voltage AVref 0 3 to AVCC 0 3 Analog power supply voltage Bus driver po...

Page 880: ...to AVCC VSS AVSS 2 0 V Item Symbol Min Typ Max Unit Test Conditions VT VCC 0 2 V VT VCC 0 7 Schmitt trigger input voltage P67 to P60 KWUL 00 3 4 IRQ7 to IRQ0 3 IRQ15 to IRQ8 KIN9 KIN8 WUE15 to WUE8 VT...

Page 881: ...and input pins other than applicable pins when IIC USB and MCIF are used VIL 0 3 VCC 0 2 VCC 0 5 IOH 200 A All output pins except for port 8 and applicable output pins when USB and MCIF are used 5 6...

Page 882: ...o VCC 0 5 V Ports 1 to 3 5 150 Ports 6 P6PUE 0 A 30 300 Input pull up MOS current Port 6 P6PUE 1 IP 3 100 A Vin 0 V RES 80 Vin 0 V NMI 50 f 1 MHz P80 to P83 4 20 Input capacitance Input pins other tha...

Page 883: ...V to the AVCC and AVref pins by connection to the power supply VCC The relationship between these two pins should be AVref AVCC 3 Includes peripheral module inputs multiplexed on the pin 4 Maximum vol...

Page 884: ...ut pins IOL 1 Total of ports 1 to 3 40 Permissible output low current total Total of all output pins including the above IOL 60 Permissible output high current per pin All output pins IOH 2 Permissibl...

Page 885: ...SDA1 and SDA0 bus drive function selected Item Symbol Min Typ Max Unit Test Conditions VT VCC 0 3 VT VCC 0 7 Schmitt trigger input voltage VT VT VCC 0 05 Input high voltage VIH VCC 0 7 VCC 0 5 Input l...

Page 886: ...8 2 5 USEXCL VCC 0 7 Input high voltage Driver receiver VIH 2 0 DrVCC 0 3 USEXCL 0 3 VCC 0 2 Input low voltage Driver receiver VIL 0 3 0 8 Including VDI Output high voltage Driver receiver VOH 2 8 3...

Page 887: ...D MCDAT MCTxD MCRxD MCCMDDIR MCDATDIR ExMCCLK ExMCCSA ExMCCSB ExMCCMD ExMCDAT ExMCTxD ExMCRxD ExMCCMDDIR ExMCDATDIR Item Symbol Min Typ Max Unit Input high voltage VIH VCC 0 625 Input low voltage VIL...

Page 888: ...834 of 872 REJ09B0286 0300 29 3 AC Characteristics Figure 29 3 shows the test conditions for the AC characteristics 3 V RL I O timing test levels Low level 0 8 V High level 1 5 V RH C LSI output pin C...

Page 889: ...VCC 3 0 V to 3 6 V VSS 0 V 5 MHz to 25 MHz Condition B VCC 2 7 V to 3 6 V VSS 0 V 5 MHz to 20 MHz Condition A Condition B Item Symbol Min Max Min Max Unit Reference Clock cycle time tcyc 40 200 50 200...

Page 890: ...2006 page 836 of 872 REJ09B0286 0300 tOSC1 tOSC1 EXTAL VCC STBY RES tDEXT tDEXT Figure 29 5 Oscillation Stabilization Timing tOSC2 NMI IRQi i 15 to 0 KINi i 9 to 0 WUEi i 15 to 8 Figure 29 6 Oscillati...

Page 891: ...Condition B VCC 2 7 V to 3 6 V VSS 0 V 5 MHz to 20 MHz Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions RES setup time tRESS 200 200 ns RES pulse width tRESW 20 20 tcyc Figure...

Page 892: ...of 872 REJ09B0286 0300 tRESW tRESS tRESS RES Figure 29 7 Reset Input Timing tIRQS IRQ edge input tIRQH tIRQH tNMIS tNMIH tIRQS IRQ level input NMI IRQi i 15 to 0 tNMIW tIRQW KIN WUE edge input KINi i...

Page 893: ...10 CS delay time IOS CS256 CPCS1 CPCS2 tCSD 15 15 AS delay time tASD 15 15 RD delay time 1 tRSD1 15 15 RD delay time 2 tRSD2 15 15 Read data setup time tRDS 15 15 Read data hold time tRDH 0 0 Read da...

Page 894: ...AS tRSD2 tAS tAH tACC2 tRSD1 tASD tASD tAD tACC3 tRDH tWRD2 tWRD2 tWSW1 tWDD tWDH tAH T1 T2 RD Read D15 to D0 Read HWR LWR Write D15 to D0 Write tRDS tAS tAS tCSD Note AS is multiplexed with IOS Eith...

Page 895: ...tASD tASD tAD tACC5 tRDH tWRD2 tWRD1 tWSW2 tWDD tWDH T1 T3 RD Read D15 to D0 Read HWR LWR Write D15 to D0 Write tWDS T2 tRDS tAH tAS Note AS is multiplexed with IOS Either the AS or IOS function can b...

Page 896: ...0 AS tWTH T1 T2 RD Read D15 to D0 Read HWR LWR Write D15 to D0 Write WAIT Tw T3 tWTS tWTH tWTS Note AS is multiplexed with IOS Either the AS or IOS function can be selected by the IOSE bit of SYSCR A1...

Page 897: ...286 0300 CPCS1 CPCS2 P92 P91 T1 T2 CPOE P93 Read Write CPD15 to CPD0 P37 to P30 CPWE P94 CPD15 to CPD0 P37 to P30 T3 tAD tAS tAS tCSD tACC4 tRSD2 tRSD1 tACC5 tRDS tAH tRDH tWRD1 tWRD2 tWSW2 tWDD tWDH...

Page 898: ...B0286 0300 AS tRSD2 tAS tAH tASD tASD tAD tACC3 tRDS tRDH T1 T2 RD Read D15 to D0 Read T2 or T3 T1 Note AS is multiplexed with IOS Either the AS or IOS function can be selected by the IOSE bit of SYSC...

Page 899: ...cted by the IOSE bit of SYSCR A17 to A0 IOS CS256 CPCS1 Figure 29 14 Burst ROM Access Timing 1 State Access 29 3 4 Timing of On Chip Peripheral Modules Tables 29 10 to 29 14 show the on chip periphera...

Page 900: ...ut delay time tTMOD 40 50 Figure 29 18 Timer reset input setup time tTMRS 30 40 ns Figure 29 20 Timer clock input setup time tTMCS 30 40 Figure 29 19 Single edge tTMCWH 1 5 1 5 TMR Timer clock pulse w...

Page 901: ...2 REJ09B0286 0300 Ports 1 to 9 and A read tPRS T1 T2 tPWD tPRH Ports 1 to 6 8 9 and A write Figure 29 15 I O Port Input Output Timing tFTIS tFTOD FTOA FTOB FTIA FTIB FTIC FTID Figure 29 16 FRT Input O...

Page 902: ...tTMOD TMO0 TMO1 TMOX TMOY Figure 29 18 8 Bit Timer Output Timing tTMCS tTMCS TMI0 TMI1 TMIX TMIY tTMCWH tTMCWL Figure 29 19 8 Bit Timer Clock Input Timing tTMRS TMI0 TMI1 TMIX TMIY Figure 29 20 8 Bit...

Page 903: ...CKf Figure 29 22 SCK Clock Input Timing SCK2 to SCK0 TxD2 to TxD0 transmit data RxD2 to RxD0 receive data tTXD tRXH tRXS Figure 29 23 SCI Input Output Timing Clock Synchronous Mode tTRGS ADTRG Figure...

Page 904: ...pulse width tSCLL 5 SCL SDA input rise time tSr 7 5 tcyc SCL SDA input fall time tSf 300 SCL SDA output fall time tOf 20 0 1 Cb 250 SCL SDA input spike pulse elimination time tSP 1 ns SDA input bus f...

Page 905: ...29 26 I2 C Bus Interface Input Output Timing Table 29 12 USB Timing Conditions VCC 3 3 V 0 3 V DrVCC 3 3 V 0 3 V DrVSS VSS 0 V Pin Functions Driver receiver input output USDP USDM USEXCL Item Symbol M...

Page 906: ...est Conditions MCCLK cycle time tPP 0 20 0 5 MHz MCCLK high pulse width tWH 10 50 MCCLK low pulse width tWL 10 50 MCCLK rise time tTLH 10 50 MCCLK fall time tTHL 10 50 ns Figure 29 28 Note Total load...

Page 907: ...9B0286 0300 ExMCCLK MCCLK ExMCCLK MCCLK ExMCCSA MCCSA ExMCCSB MCCSB ExMCCMD MCCMD ExMCDAT MCDAT ExMCRxD MCRxD ExMCCMD MCCMD ExMCDAT MCDAT ExMCTxD MCTxD ExMCCMDDIR MCCMDDIR ExMCDATDIR MCDATDIR tHOD tLO...

Page 908: ...ime tTCKcyc 40 500 ETCK clock high pulse width tTCKH 15 ETCK clock low pulse width tTCKL 15 ETCK clock rise time tTCKr 5 ETCK clock fall time tTCKf 5 ns Figure 29 29 ETRST pulse width tTRSTW 20 Reset...

Page 909: ...2006 page 855 of 872 REJ09B0286 0300 ETRST ETCK RES tRSTHW tTRSTW Figure 29 30 Reset Hold Timing ETDO Other instructions ETDO Six instructions defined in IEEE1149 1 ETDI ETMS ETCK tTMSH tTMSS tTDIH tT...

Page 910: ...AVCC VSS AVSS 0 V 5 MHz to 25 MHz Condition B VCC 2 7 V to 3 6 V AVCC 2 7 V to 3 6 V AVref 2 7 V to AVCC VSS AVSS 0 V 5 MHz to 20 MHz Condition A Condition B Item Min Typ Max Min Typ Max Unit Resoluti...

Page 911: ...V to 3 6 V AVCC 2 7 V to 3 6 V AVref 2 7 V to AVCC VSS AVSS 0 V 5 MHz to 20 MHz Condition A Condition B Item Min Typ Max Min Typ Max Unit Resolution 10 10 10 10 10 10 Bits Conversion time 5 36 6 7 s...

Page 912: ...D A Conversion Characteristics Condition A VCC 3 0 V to 3 6 V AVCC 3 0 V to 3 6 V AVref 3 0 V to AVCC VSS AVSS 0 V 5 MHz to 25 MHz Condition B VCC 2 7 V to 3 6 V AVCC 2 7 V to 3 6 V AVref 2 7 V to AVC...

Page 913: ...Wait time after P bit setting 1 4 z3 8 10 12 Additional programming Wait time after P bit clear 1 5 Wait time after PSU bit clear 1 5 Wait time after PV bit setting 1 4 Wait time after dummy write 1...

Page 914: ...tP max with referencing the actual z1 z2 and z3 settings The wait time after P bit setting z1 z2 and z3 should be changed depending on the programming count n Programming count n 1 n 6 z1 30 s z3 10...

Page 915: ...port Port 23 A11 CPREG 2 3 EXPE 1 T T kept kept kept kept Address output CPREG I O port Address output CPREG I O port 2 3 EXPE 0 I O port I O port Port 22 to 20 A10 to A8 CPA10 to CPA8 2 3 EXPE 1 T T...

Page 916: ...CPWE RD CPOE AS IOS HWR CPWE RD CPOE Port 95 to 93 AS IOS HWR CPWE RD CPOE 2 3 EXPE 0 kept kept kept kept I O port I O port Port 92 91 CPCS1 CPCS2 2 3 EXPE 1 T T kept kept kept kept CPCS1 CPCS2 I O po...

Page 917: ...Appendix Rev 3 00 Jan 25 2006 page 863 of 872 REJ09B0286 0300 B Product Lineup Product Type Type Code Mark Code Package Code H8S 2158 F ZTAT version HD64F2158 F2158VBQ25 112 pin TFBGA TBP 112A...

Page 918: ...Millimeters Symbol Reference A b x y 10 00 0 10 0 80 0 45 0 50 0 55 0 35 0 40 0 45 1 20 10 00 0 08 v w 1 00 1 00 y1 0 2 0 30 0 20 Previous Code JEITA Package Code RENESAS Code TBP 112A TBP 112AV 0 2g...

Page 919: ...rea 118 Basic Operation Timing 125 135 138 basic pulse 270 Bit Manipulation Instructions 39 bit rate 405 blanking waveform 372 Block Data Transfer Instructions 43 Block Transfer Mode 159 Boot Mode 728...

Page 920: ...ended Control Register 27 External Clock 763 External Trigger 708 FIFO empty 202 FIFO full 202 FIFO overread 202 FIFO overwrite 202 flash memory 717 framing error 427 General Registers 26 Hardware Pro...

Page 921: ...rd Interface MCIF 627 Multiprocessor Communication Function 431 NMI Interrupt 84 Normal Mode 20 122 157 Number of DTC Execution States 163 Number of FIFO Bytes 174 On Board Programming 727 Operating M...

Page 922: ...797 808 818 DTCERB 150 797 808 818 DTCERC 150 797 808 818 DTCERD 150 797 808 818 DTCERE 150 797 808 818 DTCRA 173 795 807 817 DTCRB 175 795 807 817 DTCRC 180 DTCRD 181 795 807 817 DTIDR 178 795 807 81...

Page 923: ...6 808 818 ISCRL 80 796 808 818 ISR 82 796 808 818 ISR16 82 797 808 819 ISSR 259 797 808 819 ISSR16 258 797 808 819 KBCOMP 703 796 808 KMIMR6 83 802 813 823 KMIMRA 83 802 813 823 KMPCR6 234 802 813 823...

Page 924: ...1 SYSCR2 235 775 797 809 819 TBCR 636 792 804 815 TBNCR 636 792 804 815 TCNT 320 375 799 801 811 812 820 822 TCONRI 348 803 814 823 TCONRO 352 803 814 823 TCONRS 354 803 814 823 TCORA 320 800 812 821...

Page 925: ...lave address 517 Slave Receive Operation 522 Slave Transmit Operation 525 Sleep Mode 782 Smart Card Interface 445 Software Protection 737 Software Standby Mode 782 SPI Mode 675 stack pointer SP 26 Sta...

Page 926: ...Index Rev 3 00 Jan 25 2006 page 872 of 872 REJ09B0286 0300...

Page 927: ...ication Date 1st Edition September 2001 Rev 3 00 January 25 2006 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication...

Page 928: ...esas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2730 6071 Renesas Technology Taiwan Co Ltd 1...

Page 929: ...1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan 16 H8S 2158 Group H8S 2158 F ZTATTM REJ09B0286 0300 Hardware Manual...

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