Renesas H8S/2158, User Manual

Page: 167 / 929

Section 6 Bus Controller
Rev. 3.00 Jan 25, 2006 page 113 of 872
REJ09B0286-0300
Bit Bit Name Initial Value R/W Description
2
1
0 WC22
WC21
WC20 1
1
1 R/W
R/W
R/W CP/CF Expansion Area Wait Count 2
−
0
Select the number of program wait states to be inserted
for access to the CP/CF expansion area when the
CPCSE and ASTCP bits in BCR2 are set to 1.
If the CP expansion area is selected, the WC22 bit must
be cleared to 0.
000: Program wait state is not inserted
001: 1 program wait state is inserted
010: 2 program wait states are inserted
011: 3 program wait states are inserted
100: 4 program wait states are inserted (only for CF
expansion area)
101: 6 program wait states are inserted (only for CF
expansion area)
110: 8 program wait states are inserted (only for CF
expansion area)
111: 10 program wait states are inserted (only for CF
expansion area)
6.4 Bus Control
6.4.1 Bus Specifications
The external address space bus specifications consist of three elements: Bus width, the number of
access states, and the wait mode and the number of program wait states. The bus width and the
number of access states for on-chip memory and internal I/O registers are fixed, and are not
affected by the bus controller settings.
Bus Width: A bus width of 8 or 16 bits can be selected via the ABW and ABW256 bits in WSCR,
and the ABWCP bit in BCR2. If memory card mode is selected when the CFE bit in BCR is set to
1, a 16-bit bus is automatically selected for CP expansion area access.
Number of Access States: Two or three access states can be selected via the AST and AST256
bits in WSCR, and the ASTCP bit in BCR2. When the 2-state access space is designated, wait-
state insertion is disabled.
In the burst ROM interface, the number of access states for the basic expansion area is determined
regardless of the AST bit setting.