Renesas H8S/2158, User Manual

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Section 18 Universal Serial Bus Interface (USB)
Rev. 3.00 Jan 25, 2006 page 557 of 872
REJ09B0286-0300
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USB port control register (UPRTCR)
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USB test register 0 (UTESTR0)
•
USB test register 1 (UTESTR1)
18.3.1 USB Data FIFO
FIFOs combined with EPDRs intervene in data transfer between this LSI (slave CPU) and the
USB function core. The USB function core performs data transmission to or from the USB host
(host).
This LSI incorporates 80 bytes of specific FIFOs, and a RAM-FIFO unit (RFU) that can be used
as a maximum of 4096 bytes of FIFOs by using on-chip RAM.
As shown in table 18.2, specific FIFOs can be used in two ways based on whether EP2 is used or
not. In EP0I, EP0O, EP1, and EP2, the maximum packed size of the data packet is specified as
half of the FIFO size (bytes). In EP0S and EP3, the maximum packet size of the data packet is
equal to the FIFO size (bytes). EP0S is a specific FIFO for setup command reception, which is
enabled or disabled by the SETICNT bit in USBMDCR. For details on RAM-FIFOs that form
EP4 and EP5, refer to section 8, RAM-FIFO Unit (RFU).
In the host input transfer, all data items sent from the slave are written to a specific FIFO before
the slave transmission is initiated. In the host output transfer, the host transfer is completed before
the slave reads all data items from the specific FIFO.
Table 18.2 FIFO Configuration
Endpoint Transfer Direction FIFO Size Configuration Description
EP0S OUT (SETUP) 8 bytes 8 bytes × 1
EP0O OUT 16 bytes 8 bytes × 2
Endpoint 0
EP0I IN 16 bytes 8 bytes × 2
Endpoint 1 EP1 IN 16 bytes 8 bytes × 2
32 bytes 16 bytes × 2
Endpoint 2 EP2 IN/OUT 16 bytes 8 bytes × 2
0 bytes Not used
Endpoint 3 EP3 IN 8 bytes 8 bytes × 1
Specific FIFO
Endpoint 4 EP4 IN Max. 2048 bytes Max. 64 bytes
× 32
Endpoint 5 EP5 OUT Max. 2048 bytes Max. 64 bytes
× 32
RAM-FIFO
(RFU)