Section 18 Universal Serial Bus Interface (USB)
Rev. 3.00 Jan 25, 2006 page 570 of 872
REJ09B0286-0300
Bit
Bit Name Initial Value R/W
Description
1
SPNDIF
0
R/(W)
*
Suspend IN Interrupt Status
Indicates that the USB function core detects an idle state
for a specific period or more, and detects a bus state
transition from normal state to suspend state.
If the SPNDE bit in USBIER0 is set to 1, an USBID
interrupt is requested to the slave CPU.
[Clearing condition]
•
0 is written to after SPNDIF = 1 has been read.
[Setting condition]
•
The USB function core detects s bus state transition
from normal state to suspend state.
0
SETUPF
0
R/(W)
*
Setup Interrupt Status
The meaning of this bit differs depending on the
SETICNT bit in USBMDCR.
When SETICNT = 0, Indicates that endpoint 0 of the
USB function core receives a SETUP token.
When SETICNT = 1, Indicates that endpoint 0 of the
USB function core receives a setup command that must
be decoded by the slave CPU.
If the SETUPE bit in USBIER0 is set to 1, an USBIA
interrupt is requested to the slave CPU.
[Clearing condition]
•
0 is written to after SETUPF = 1 has been read.
[Setting conditions]
•
Endpoint 0 of the USB function core receives a
SETUP token (when SETICNT = 0).
•
Endpoint 0 of the USB function core receives a setup
command to be decoded by the slave CPU (when
SETICNT = 1).
Note:
*
Only 0 can be written to clear the flag.
Summary of Contents for H8S/2158
Page 10: ...Rev 3 00 Jan 25 2006 page viii of lii...
Page 36: ...Rev 3 00 Jan 25 2006 page xxxiv of lii B Product Lineup 863 C Package Dimensions 864 Index 865...
Page 47: ...Rev 3 00 Jan 25 2006 page xlv of lii Appendix Figure C 1 Package Dimensions TBP 112A 864...
Page 54: ...Rev 3 00 Jan 25 2006 page lii of lii...
Page 70: ...Section 1 Overview Rev 3 00 Jan 25 2006 page 16 of 872 REJ09B0286 0300...
Page 118: ...Section 3 MCU Operating Modes Rev 3 00 Jan 25 2006 page 64 of 872 REJ09B0286 0300...
Page 126: ...Section 4 Exception Handling Rev 3 00 Jan 25 2006 page 72 of 872 REJ09B0286 0300...
Page 198: ...Section 6 Bus Controller Rev 3 00 Jan 25 2006 page 144 of 872 REJ09B0286 0300...
Page 326: ...Section 10 8 Bit PWM Timer PWM Rev 3 00 Jan 25 2006 page 272 of 872 REJ09B0286 0300...
Page 440: ...Section 15 Watchdog Timer WDT Rev 3 00 Jan 25 2006 page 386 of 872 REJ09B0286 0300...
Page 606: ...Section 17 I 2 C Bus Interface IIC Rev 3 00 Jan 25 2006 page 552 of 872 REJ09B0286 0300...
Page 742: ...Section 19 Multimedia Card Interface MCIF Rev 3 00 Jan 25 2006 page 688 of 872 REJ09B0286 0300...
Page 750: ...Section 21 D A Converter Rev 3 00 Jan 25 2006 page 696 of 872 REJ09B0286 0300...
Page 768: ...Section 22 A D Converter Rev 3 00 Jan 25 2006 page 714 of 872 REJ09B0286 0300...
Page 770: ...Section 23 RAM Rev 3 00 Jan 25 2006 page 716 of 872 REJ09B0286 0300...
Page 824: ...Section 26 Clock Pulse Generator Rev 3 00 Jan 25 2006 page 770 of 872 REJ09B0286 0300...
Page 844: ...Section 27 Power Down Modes Rev 3 00 Jan 25 2006 page 790 of 872 REJ09B0286 0300...
Page 878: ...Section 28 List of Registers Rev 3 00 Jan 25 2006 page 824 of 872 REJ09B0286 0300...
Page 926: ...Index Rev 3 00 Jan 25 2006 page 872 of 872 REJ09B0286 0300...