Renesas H8S/2158, User Manual

Page: 820 / 929

Section 26 Clock Pulse Generator
Rev. 3.00 Jan 25, 2006 page 766 of 872
REJ09B0286-0300
26.3 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock (
φ
), and generates
φ
/2,
φ
/4,
φ
/8,
φ
/16,
and
φ
/32 clocks.
26.4 Bus Master Clock Select Circuit
The bus master clock select circuit selects a clock to supply the bus master with either the system
clock (
φ
) or medium-speed clock (
φ
/2,
φ
/4,
φ
/8,
φ
/16, or
φ
/32) by the SCK2 to SCK0 bits in
SBYCR.
26.5 Subclock Input Circuit
The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a
32.768-kHz external clock should be input from the EXCL pin. At this time, the P96DDR bit in
P9DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1.
Subclock input conditions are shown in table 26.5. When the subclock is not used, subclock input
should not be enabled.
Table 26.5 Subclock Input Conditions
VCC = 2.7 to 3.6 V
Item Symbol
Min Typ Max
Unit
Measurement
Condition
Subclock input pulse width
low level t
EXCLL
— 15.26 —
µ
s
Subclock input pulse width
high level t
EXCLH
— 15.26 —
µ
s
Subclock input rising time t
EXCLr
— — 10 ns
Subclock input falling time t
EXCLf
— — 10 ns
Figure 26.7