Section 18 Universal Serial Bus Interface (USB)
Rev. 3.00 Jan 25, 2006 page 609 of 872
REJ09B0286-0300
USB Host
Send an OUT data
packet (8 bytes)
Receive an ACK
handshake packet
USB Function Core
Slave CPU
Core Interface
Automatically set
each flag
*
1
Write data to EP0S FIFO
Command data decode
Check if decode by
the slave CPU is required
or not
Send ACK to
the host
Send ACK to
the slave CPU
Modify FVSR0S
Request an USBIA
interrupt (SETUPF)
Initiate the USBIA
interrupt processing
Read USBIFR0
*
2
Notes: 1. Set the EP0OTC bit of USECSR0 to 1, initialize FVSR0S, FVSR0I, and FVSR0O, clear the EP0ITS and EP0OTS bits of TSFR0 to 0,
clear the EP0ITF and EP0OTF bits of TFFR0 to 0, and clear the EP0STL bit of EPSTLR0 to 0.
2. Since a USBIA interrupt is only assigned to a SETUP interrupt, interrupt source determination process is not required.
Send a SETUP
token packet
Receive a SETUP
token packet
Receive an OUT data
packet (8 bytes)
Clear the SETUPF bit of
USBIFR0 to 0
Complete the USBIA
interrupt processing
Read EPDR0S
Set the EP0OTC bit of
USBCSR0 to 1
(write 1 to EP0OTC after
EP0OTC = 1 was read)
Check the instruction
by data decode
Read FVSR0S and check
if the EP0S FIFO
contains 8-byte data
Figure 18.5 Operation on Receiving a SETUP Token (When Decode by the Slave CPU Is
Required and When SETICNT = 1)
Summary of Contents for H8S/2158
Page 10: ...Rev 3 00 Jan 25 2006 page viii of lii...
Page 36: ...Rev 3 00 Jan 25 2006 page xxxiv of lii B Product Lineup 863 C Package Dimensions 864 Index 865...
Page 47: ...Rev 3 00 Jan 25 2006 page xlv of lii Appendix Figure C 1 Package Dimensions TBP 112A 864...
Page 54: ...Rev 3 00 Jan 25 2006 page lii of lii...
Page 70: ...Section 1 Overview Rev 3 00 Jan 25 2006 page 16 of 872 REJ09B0286 0300...
Page 118: ...Section 3 MCU Operating Modes Rev 3 00 Jan 25 2006 page 64 of 872 REJ09B0286 0300...
Page 126: ...Section 4 Exception Handling Rev 3 00 Jan 25 2006 page 72 of 872 REJ09B0286 0300...
Page 198: ...Section 6 Bus Controller Rev 3 00 Jan 25 2006 page 144 of 872 REJ09B0286 0300...
Page 326: ...Section 10 8 Bit PWM Timer PWM Rev 3 00 Jan 25 2006 page 272 of 872 REJ09B0286 0300...
Page 440: ...Section 15 Watchdog Timer WDT Rev 3 00 Jan 25 2006 page 386 of 872 REJ09B0286 0300...
Page 606: ...Section 17 I 2 C Bus Interface IIC Rev 3 00 Jan 25 2006 page 552 of 872 REJ09B0286 0300...
Page 742: ...Section 19 Multimedia Card Interface MCIF Rev 3 00 Jan 25 2006 page 688 of 872 REJ09B0286 0300...
Page 750: ...Section 21 D A Converter Rev 3 00 Jan 25 2006 page 696 of 872 REJ09B0286 0300...
Page 768: ...Section 22 A D Converter Rev 3 00 Jan 25 2006 page 714 of 872 REJ09B0286 0300...
Page 770: ...Section 23 RAM Rev 3 00 Jan 25 2006 page 716 of 872 REJ09B0286 0300...
Page 824: ...Section 26 Clock Pulse Generator Rev 3 00 Jan 25 2006 page 770 of 872 REJ09B0286 0300...
Page 844: ...Section 27 Power Down Modes Rev 3 00 Jan 25 2006 page 790 of 872 REJ09B0286 0300...
Page 878: ...Section 28 List of Registers Rev 3 00 Jan 25 2006 page 824 of 872 REJ09B0286 0300...
Page 926: ...Index Rev 3 00 Jan 25 2006 page 872 of 872 REJ09B0286 0300...