Renesas H8S/2158, User Manual

Page: 754 / 929

Section 22 A/D Converter
Rev. 3.00 Jan 25, 2006 page 700 of 872
REJ09B0286-0300
22.3 Register Descriptions
The A/D converter has the following registers.
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A/D data register A (ADDRA)
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A/D data register B (ADDRB)
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A/D data register C (ADDRC)
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A/D data register D (ADDRD)
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A/D control/status register (ADCSR)
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A/D control register (ADCR)
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Keyboard comparator control register (KBCOMP)
22.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown
in table 22.2.
The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0.
The data bus between the CPU and the A/D converter is 8-bit width. The upper byte can be read
directly from the CPU, but the lower byte should be read via a temporary register. The temporary
register contents are transferred from the ADDR when the upper byte data is read. When reading
the ADDR, read only the upper byte in word units.
Table 22.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Group 0 Group 1
A/D Data Register to Store A/D Conversion
Results
CIN0 to CIN7 AN4 ADDRA
— AN5 ADDRB
AN2 AN6 ADDRC
AN3 AN7 ADDRD