Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
Rev. 3.00 Jan 25, 2006 page 391 of 872
REJ09B0286-0300
16.2
Input/Output Pins
Table 16.1 shows the input/output pins for each SCI channel.
Table 16.1 Pin Configuration
Channel
Symbol
*
Input/Output
Function
SCK0
Input/Output
Channel 0 clock input/output
RxD0
Input
Channel 0 receive data input
TxD0
Output
Channel 0 transmit data output
0
SSE0I
Input
Channel 0 stop input
SCK1
Input/Output
Channel 1 clock input/output
RxD1/IrRxD
Input
Channel 1 receive data input (normal/IrDA)
1
TxD1/IrTxD
Output
Channel 1 transmit data output (normal/IrDA)
SCK2
Input/Output
Channel 2 clock input/output
RxD2
Input
Channel 2 receive data input
TxD2
Output
Channel 2 transmit data output
2
SSE2I
Input
Channel 2 stop input
Note:
*
Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the
channel designation.
16.3
Register Descriptions
The SCI has the following registers for each channel. Some bits in the serial mode register (SMR),
serial status register (SSR), and serial control register (SCR) have different functions in different
modes—normal serial communication interface mode and smart card interface mode; therefore,
the bits are described separately for each mode in the corresponding register sections.
•
Receive shift register (RSR)
•
Receive data register (RDR)
•
Transmit data register (TDR)
•
Transmit shift register (TSR)
•
Serial mode register (SMR)
•
Serial control register (SCR)
•
Serial status register (SSR)
•
Smart card mode register (SCMR)
•
Bit rate register (BRR)
Summary of Contents for H8S/2158
Page 10: ...Rev 3 00 Jan 25 2006 page viii of lii...
Page 36: ...Rev 3 00 Jan 25 2006 page xxxiv of lii B Product Lineup 863 C Package Dimensions 864 Index 865...
Page 47: ...Rev 3 00 Jan 25 2006 page xlv of lii Appendix Figure C 1 Package Dimensions TBP 112A 864...
Page 54: ...Rev 3 00 Jan 25 2006 page lii of lii...
Page 70: ...Section 1 Overview Rev 3 00 Jan 25 2006 page 16 of 872 REJ09B0286 0300...
Page 118: ...Section 3 MCU Operating Modes Rev 3 00 Jan 25 2006 page 64 of 872 REJ09B0286 0300...
Page 126: ...Section 4 Exception Handling Rev 3 00 Jan 25 2006 page 72 of 872 REJ09B0286 0300...
Page 198: ...Section 6 Bus Controller Rev 3 00 Jan 25 2006 page 144 of 872 REJ09B0286 0300...
Page 326: ...Section 10 8 Bit PWM Timer PWM Rev 3 00 Jan 25 2006 page 272 of 872 REJ09B0286 0300...
Page 440: ...Section 15 Watchdog Timer WDT Rev 3 00 Jan 25 2006 page 386 of 872 REJ09B0286 0300...
Page 606: ...Section 17 I 2 C Bus Interface IIC Rev 3 00 Jan 25 2006 page 552 of 872 REJ09B0286 0300...
Page 742: ...Section 19 Multimedia Card Interface MCIF Rev 3 00 Jan 25 2006 page 688 of 872 REJ09B0286 0300...
Page 750: ...Section 21 D A Converter Rev 3 00 Jan 25 2006 page 696 of 872 REJ09B0286 0300...
Page 768: ...Section 22 A D Converter Rev 3 00 Jan 25 2006 page 714 of 872 REJ09B0286 0300...
Page 770: ...Section 23 RAM Rev 3 00 Jan 25 2006 page 716 of 872 REJ09B0286 0300...
Page 824: ...Section 26 Clock Pulse Generator Rev 3 00 Jan 25 2006 page 770 of 872 REJ09B0286 0300...
Page 844: ...Section 27 Power Down Modes Rev 3 00 Jan 25 2006 page 790 of 872 REJ09B0286 0300...
Page 878: ...Section 28 List of Registers Rev 3 00 Jan 25 2006 page 824 of 872 REJ09B0286 0300...
Page 926: ...Index Rev 3 00 Jan 25 2006 page 872 of 872 REJ09B0286 0300...