Renesas H8S/2158, User Manual

Page: 647 / 929

Section 18 Universal Serial Bus Interface (USB)
Rev. 3.00 Jan 25, 2006 page 593 of 872
REJ09B0286-0300
Bit Bit Name Initial Value R/W Description
1 FPLLRST 1 R/W Function PLL Software Reset
Resets the USB bus clock circuit (DPLL) in the USB
function core.
Setting this bit to 1 resets the DPLL in the USB function
core and stops bus clock synchronization. Clear this bit
to 0 after the PLL operation is stabilized.
0: Sets DPLL in operating state.
1: Sets DPLL in reset state.
0 FSRST 1 R/W Function Core Internal State Software Reset
Resets the internal state of the USB function core.
Setting this bit 1 to 1 initializes all the internal states of
the USB function core other than the bus clock circuit
(DPLL). Clear this bit to 0 after the DPLL operation is
stabilized.
A function software reset is defined as the state where
both the FSRST and UIFRST bits are set to 1.
0: Sets USB function core other than DPLL in operating
state.
1: Sets USB function core other than DPLL in reset
state.