Renesas H8S/2158, User Manual

Page: 696 / 929

Section 19 Multimedia Card Interface (MCIF)
Rev. 3.00 Jan 25, 2006 page 642 of 872
REJ09B0286-0300
Bit Bit Name Initial Value R/W Description
4 DATAEN 0 R/W Data Enable
Read as 1 during data transfer period after 1 is
written. Otherwise, read as 0. Starts write data
transmission by a command with write data.
Resumes transfer clock output and write data
transmission when the transfer clock is halted
according to FIFO empty or termination of one
block writing in multiblock write.
Write enable period:
•
After transmission of a command with write
data
•
While transfer clock is halted according to
FIFO empty
•
When one block writing in multiblock write
is terminated
0: Operation is not affected.
1: Starts or resumes transfer clock output and
write data transmission.
3 to
0 — All 0 R/(W) Reserved
The initial value should not be changed.
The command sequence on the MMC side may be halted according to the status of MMC. Table
19.5 shows the MMC states in which the command sequence is halted. In this case, the command
sequence should be aborted by setting the CMDOFF bit to 1 on the MCIF side as required.
Table 19.5 Card States in which Command Sequence Is Halted
Operating Mode Error Status
Command response When the error detection bit in the card status (32 bits) in the
command response transmitted by the MMC is set. MMC mode
Data status When the error detection bit in the CRC status (3 bits) to be
transmitted from the MMC while block data is transmitted to
the MMC is set.
Command response When the error detection bit in the card status (8 bits) in the
command response transmitted by the MMC is set. SPI mode
Data response When the error detection bit in the data response (8 bits) to
be transmitted from the MMC while block data is transmitted
to the MMC is set.