Renesas H8S/2158, User Manual

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Section 13 8-Bit Timer (TMR)
Rev. 3.00 Jan 25, 2006 page 336 of 872
REJ09B0286-0300
13.7 Input Capture Operation
TMR_X has input capture registers (TICR, TICRR and TICRF). A narrow pulse width can be
measured with TICRR and TICRF, using a single capture operation controlled by the ICST bit in
TCONRI of the timer connection. If the falling edge of TMRIX (TMR_X input capture input
signal) is detected after its rising edge has been detected while the ICST bit is set to 1, the value of
TCNT_X at that time is transferred to both TICRR and TICRF, and the ICST bit is cleared to 0.
The TMRIX input signal can be switched by the setting of the other bits in TCONRI.
Input Capture Signal Input Timing: Figure 13.11 shows the timing of the input capture
operation.
φ
TMRIX
Input capture
signal
TCNT_X n
n n
m
M
m
N + 1 N
N
n + 1
TICRR
TICRF
Figure 13.11 Timing of Input Capture Operation
If the input capture signal is input while TICRR and TICRF are being read, the input capture
signal is delayed by one system clock
(φ
) cycle. Figure 13.12 shows the timing of this operation.