Renesas H8S/2158, User Manual

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Section 8 RAM-FIFO Unit (RFU)
Rev. 3.00 Jan 25, 2006 page 190 of 872
REJ09B0286-0300
•
RFU bus cycle: 2 states
•
Cycle to synchronize the RFU signal with the peripheral module clock: 1 and 2 states
(depending on the peripheral module clock)
The total of the above cycles is 5 to 13 states. Cycles for synchronization of the peripheral module
clock with the system clock are needed even when the hardware FIFO is used instead of the RFU.
Therefore, RAM-FIFO overhead by the RFU is 3 to 10 states (except for wait states for external
extension). To reduce the RFU response time, it is recommended to set the external extension area
access to 3 states/no waits.
SB0V
* 1
SB1V
*
2
T1 T1 T1 T1 T1 T1 T2 T2 T2 T2 T2 T2
CPU bus cycle
CPU bus cycle
CPU bus cycle CPU bus cycle CPU bus cycle RFU bus cycle
φ
12-MHz clock
for the USB
RFU activation
request
RFU bus cycle
Notes: 1. USB SENDBUFCR SB0V bit: Transmit buffer 0 valid bit
2. USB SENDBUFCR SB1V bit: Transmit buffer 1 valid bit
System clock
synchronization cycle
System clock
synchronizatioin
cycle
Request output
cycle
Cycle to wait
for the end of
the current
bus cycle
Synchronization
cycle with
the peripheral
module clock
RFU bus cycle
Figure 8.3 Example of RFU Response Time