IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 316 / 744

IDT DMA Controller
PES32NT24xG2 User Manual 15 - 28 January 30, 2013
Notes
PCI Express errors are those specified in the PCI Express Base specification. DMA channel errors are
additional proprietary errors associated with the operation of the DMA channels within the DMA function.
PCI Express errors are described in section PCI Express Error Handling by the DMA Function on page 15-
28.
Internal switch errors (i.e., parity errors, switch time-out, and internal memory errors) are associated with
the switch core and not with a specific port function. These errors are not described here. Refer to section
Internal Errors on page 4-16 for a detailed description of these errors.
PCI Express Error Handling by the DMA Function
The error handling described in this section corresponds to that outlined in PCI Express Base Specifica-
tion 2.1. This section describes error conditions detected by the DMA function. This includes physical, data-
link, and transaction layer errors detected by the port, as well as application layer errors associated with the
DMA function in the port.
The errors described here apply to ports that operate in a mode that includes a DMA function (e.g.,
upstream switch port with DMA function mode, NT with DMA function mode, etc.) This section focuses
specifically on PCI Express errors related to the DMA function
1
. Errors that affect all functions of the port
(i.e., non function-specific errors) are noted where appropriate.
PCI Express errors are logged in standard PCI Express registers (e.g., AER capability, PCI Status,
Device Status registers, etc.) and signaled via the mechanisms defined in PCI Express Base Specification
2.1 (e.g., correctable or uncorrectable error messages, etc).
– The terms ‘uncorrectable error processing’ and ‘correctable error processing’ refer to the
processing described in Section 6.2.5 of PCI Express Base Specification 2.1.
In cases where a PCI Express error can be correlated to the operation of a DMA channel (e.g., a
completion timeout when a DMA channel reads a descriptor), or when a PCI Express error causes one or
all DMA channels to abort operation, additional error log bits are provided in the corresponding DMA
Channel Error Status (DMACxERRSTS) register. This section describes all such cases.
– Errors logged in the DMACxERRSTS register may cause the DMA function to generate an inter-
rupt as described in section Channel Interrupts on page 15-21. Individual errors may be masked
from generating an interrupt by programming the appropriate bit(s) in the DMA Channel Error
Mask (DMACxERRMSK) register.
For some of the errors listed in this section, detection of the error causes the DMA channel to abort
processing of the current descriptor. When this occurs, the actions described in section Aborting a DMA
Operation on page 15-18 take place.
Additional Notes Regarding PCI Express Errors
Some of the errors described in this section are non function-specific. Errors that are not function-
specific are logged in the corresponding status and logging registers of all functions in the port. Errors that
are function-specific are logged in the status & logging register of the affected function. Signaling of non
function-specific errors follows the rules in Section 6.2.4 of PCI Express Base Specification 2.1.
For example, depending on the operating mode of the port, the DMA function may share the upstream
port of a partition with the PCI-to-PCI bridge function (i.e., the upstream port is a multi-function port). Errors
that are non function-specific would be logged and signaled by all functions of the port, per the rules in
Section 6.2.4 of PCI Express Base Specification 2.1. Errors that are specific to the DMA function would only
be logged in the configuration space registers of the DMA function.
1.
Errors associated with the NT function (i.e., non-transparent operation errors) are described in Chapter 14.
Errors associated with the PCI-to-PCI bridge function are described in Chapter 10.