IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 713 / 744

IDT Usage Models
PES32NT24xG2 User Manual 26 - 3 January 30, 2013
Notes
Figure 26.2 PES24NT6AG2 with Ports Operating in Different Clock Modes
Description
By default, all ports operate in global clocked mode. The CLKMODE[1:0] pins in the boot vector should
be set to 0x1 to indicate that the upstream port of the switch operates in a common-clocked configuration
with its link partner, while the downstream ports operate in a non-common clocked configuration with its link
partner. Refer to Table 2.5.
Port 12 operates in a non-common clocked configuration with its link partner. Therefore, the serial
EEPROM instruction sequence should clear the SCLK field in the PCI Express Link Status (PCIELSTS) of
port 12. Follow the guidelines outlined in the implementation note entitled “Use of the Slot Clock Configura-
tion and Common Clock Configuration Bits” in the PCI Express Base Specification 2.1.
To place the upstream port (port 0) in local port clocked mode, the serial EEPROM instruction sequence
programs the P0CLKMODE field in the PCLKMODE register to select local port clocking mode.
– In response, the switch automatically changes the port’s clock mode using the sequence
described in section Port Clocking Mode Selection on page 2-6.
– If port 0’s link was up at the time the EEPROM modifies the port’s clocking mode, the link transi-
tions to the Detect state.
– After the hardware modifies the port’s clock mode, port 0’s link is automatically retrained.
With this configuration, port 0 and its link partner (e.g., a root-complex port) operate using the same
reference clock, which is separate from the global clocked used by the switch downstream ports. Further,
the reference clock used by the upstream port may have Spread Spectrum Clocking (SSC) as long as the
switch’s global reference clock does not. Finally, port 12 operates in a non-common clocked configuration,
while the other downstream ports operate in a common-clocked configuration.
Boot-time Switch Partitioning
This section describes examples of switch partitioning. The examples described here rely on the
concepts and functionality described in Chapter 5, Switch Partition and Port Configuration.
PES24NT6AG2
Serial
EEPROM
P0
P4 P6
Root Complex
P8
Ref
Clk
EP EP EP
GCLK
P12
EP
Ref
Clk
Ref
Clk
CLKMODE[1:0]
SSC