IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 616 / 744

IDT DMA Function Registers
PES32NT24xG2 User Manual 23 - 28 January 30, 2013
Notes
AERUEM - AER Uncorrectable Error Mask (0x108)
21 ACSV RW1C 0x0
Sticky
ACS Violation Status.
This bit is set when an ACS violation is detected by this
function.
22 UIE RW1C 0x0
Sticky
Uncorrectable Internal Error Status.
This bit is set when an uncorrectable internal error associ-
ated with the this function is detected.
When the Internal Error Reporting Enable (IERROREN) bit
is cleared in the Internal Error Reporting Control (IER-
RORCTL) register, this field becomes read-only with a
value of zero.
The IERRORCTL register is a proprietary register located in
the configuration space of the port’s PCI-to-PCI bridge
function. Refer to section Proprietary Port-Specific Regis-
ters in the PCI-to-PCI Bridge Function on page 19-11 for
details.
23 MCBLKTLP RO 0x0 MC Blocked TLP Status.
Not applicable (the DMA function does not have a multicast
capability structure).
24 ATOPEB RO 0x0 AtomicOp Egress Blocked Status.
Not applicable.
25 TLPPBE RO 0x0 TLP Prefix Blocked Error Status.
Not applicable.
31:26 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
0 UDEF RW 0x0
Sticky
Undefined.
This bit is no longer used in this version of the specification.
3:1 Reserved RO 0x0 Reserved field.
4 DLPERR RW 0x0
Sticky
Data Link Protocol Error Mask.
When this bit is set, the corresponding bit in the AERUES
register is masked. When a bit is masked in the AERUES
register, the corresponding event is not logged in the AER
Header Log registers, the First Error Pointer field (FEPTR)
in the AERCTL register is not updated, and an error is not
reported to the root complex.
This bit does not affect the state of the corresponding bit in
the AERUES register.
5 SDOENERR RO 0x0 Surprise Down Error Mask.
Not applicable.
11:6 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description