IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 621 / 744

IDT DMA Function Registers
PES32NT24xG2 User Manual 23 - 33 January 30, 2013
Notes
12 RPLYTO RW1C 0x0
Sticky
Replay Timer timeout Status.
This bit is set when the replay timer in the data link layer
times out.
13 ADVISORYNF RW1C 0x0
Sticky
Advisory Non-Fatal Error Status.
This bit is set when an advisory non-fatal error is detected
as described in Section 6.2.3.2.4 of the PCI Express Base
Specification Rev 2.1.
14 CIE RW1C 0x0
Sticky
Correctable Internal Error Status.
This bit is set whenever an correctable internal error associ-
ated with the port is detected.
When the Internal Error Reporting Enable (IERROREN) bit
is cleared in the Internal Error Reporting Control (IER-
RORCTL) register, this field becomes read-only with a
value of zero.
The IERRORCTL register is a proprietary register located in
the configuration space of the port’s PCI-to-PCI bridge
function. Refer to section Proprietary Port-Specific Regis-
ters in the PCI-to-PCI Bridge Function on page 19-11 for
details.
15 HLO RW1C 0x0
Sticky
Header Log Overflow Status.
This bit is set when an error that requires packet-header
logging occurs but the packet header cannot be logged by
the function’s AER Header Log registers (AERHL[1:4]DW).
A packet’s header cannot be logged in the AER Header Log
registers when an error occurs while the First Error Pointer
(FEPTR field in the AERCTL register) is valid. The First
Error Pointer is valid when it points to a set bit in the
AERUES register (i.e., indicating the occurrence of a prior
uncorrectable error which has not been cleared by soft-
ware).
When the Internal Error Reporting Enable (IERROREN) bit
is cleared in the Internal Error Reporting Control (IER-
RORCTL) register, this field becomes read-only with a
value of zero.
The IERRORCTL register is a proprietary register located in
the configuration space of the port’s PCI-to-PCI bridge
function. Refer to section Proprietary Port-Specific Regis-
ters in the PCI-to-PCI Bridge Function on page 19-11 for
details.
31:16 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description