IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 237 / 744

IDT SMBus Interfaces
PES32NT24xG2 User Manual 12 - 33 January 30, 2013
Notes
The CSR_Offset is shifted 2 bits to the right so that DWORD aligned register offsets are only accessible;
this step may not be needed for some devices.
Read BYTE Setup
Steps 2 and 3 show how each index in the CSR byte sequence array is set for a BYTE read operation.
For step 3, the transaction size is a value that is passed to the I2C control function so that it knows how
many bytes are being dealt with in the CSR byte sequence.
Step 2. Prepare the I2C byte array
Table 12.27 shows the block byte array assignments (in increasing index order starting from index 0).
Address offset 0 is used in the examples.
Index 0 - Initialize the command code byte
CCode_i |= CCode_Block
CCode_i = 0x03 | 0x40 = 0x43
0x43 = (start bit= 1, end bit= 1, function_bits= CSR, size_bits= BLOCK)
Index 1 - Set the byte count
BKCnt_i = TranSize_BkWtHeader
BKCnt_i = 3
The byte count field indicates the number of bytes following the byte count field when setting up for a
write or setting up for a read.
Index 2 - Set the byte option (BELL) and set the CSR READ operation (OPRD)
BKCmd_i = CMD_Init | CMD_BELL | CMD_OPRD
BKCmd_i = 0x00 | 0x01 | 0x10 = 0x11
Index 3 - Set the lower CSR register offset
BKOfL_i = CSR_Offset & 0xFF
BKOfL_i = 0x00 & 0xFF = 0
Index 4 - Set the upper CSR register offset
BKOfU_i = (CSR_Offset & 0xFF00) >> 8
BKOfU_i = (0x00 & 0xFF00) >> 8 = 0
Step 3. Calculate the transaction size and read length
TranSize = TranSize_ 1
ReadLength = TranSize_BkRdHeader
Index # Assignment Description
0 CCode_i |= CCode_Block
1 BKCnt_i = TranSize_BkWtHeader
2 BKCmd_i = CMD_Init | CMD_BELL | CMD_OPRD
3 BKOfL_i = CSR_Offset & 0xFF
4 BKOfU_i = (CSR_Offset & 0xFF00) >> 8
Table 12.27 I2C Command Byte Array Indices