IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 65 / 744

Notes
PES32NT24xG2 User Manual 3 - 1 January 30, 2013
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Chapter 3
Reset and Initialization
Overview
This chapter describes the PES32NT24xG2 resets and initialization. There are two classes of switch
resets. The first is a switch fundamental reset which is the reset used to initialize the entire device. The
second class is referred to as partition resets. This second class has multiple sub-categories. Partition
resets are associated with a specific PES32NT24xG2 switch partition and correspond to those resets
defined in the PCI Express base specification (e.g., fundamental reset, hot reset, etc). Switch resets are
described in section Partition Resets on page 3-11 while partition resets are described in section Partition
Resets on page 3-11.
When multiple resets are initiated concurrently, the precedence shown in Table 3.1 is used to determine
which one is acted upon.
– Reset types and causes are described in detail in the following sections.
• A switch fundamental reset affects the entire device
• A partition reset affects the partition and ports associated with that partition
• A port reset affects only that one port
– When a high priority and low priority reset are initiated concurrently and the condition causing the
high priority reset ends prior to that causing the low priority reset, then the device/partition/port
immediately transitions to the reset associated with low priority reset condition.
• If the high priority and low priority resets share the same reset type, then the device/partition/
port remains in the corresponding reset when the high priority reset condition ends.
• If the high priority and low priority reset have different reset types, then the device/partition/port
transitions to the low priority reset type when the high priority reset condition ends.
Priority Reset Type Reset Cause
1
(Highest)
Switch fundamental reset Global reset pin (PERSTN) assertion
2 Port mode change reset Port operating mode change and OMA field set to port reset in
the corresponding SWPORTxCTL register
Partition fundamental reset Directed by STATE field value in SWPARTxCTL register
3 Partition fundamental reset Assertion of partition fundamental reset pin (PARTxPERSTN)
4 Partition hot reset Reception of TS1 ordered sets on upstream port indicating a
hot reset
5 Partition hot reset Data link layer of the upstream port transitioning to DL_Down
state
6 Partition upstream secondary
bus reset Setting of the SRESET bit in the partition’s upstream port PCI-
to-PCI bridge BCTL register
7
(Lowest)
Partition downstream secondary
bus reset Setting of the SRESET bit in the in the corresponding port’s
PCI-to-PCI bridge BCTL register
Table 3.1 PES32NT24xG2 Reset Precedence