IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 154 / 744

IDT SerDes
PES32NT24xG2 User Manual 8 - 6 January 30, 2013
Notes
SerDes Transmitter Control Registers
As described above, each switch SerDes quad is associated with two transmitter control registers
(S[x]TXLCTL0 and S[x]TXLCTL1). Together, these registers allow full programmability of the SerDes trans-
mitter voltage levels and de-emphasis. These registers are segmented into fields that allow programma-
bility of the transmit driver levels under the following PHY operating modes:
– Full-Swing Mode, in Gen 1 data rate, with -3.5 dB de-emphasis
– Full-Swing Mode, in Gen 2 data rate, with -3.5 dB de-emphasis
– Full-Swing Mode, in Gen 2 data rate, with -6.0 dB de-emphasis
– Low-Swing Mode, in Gen 1 data rate (no de-emphasis)
– Low-Swing Mode, in Gen 2 data rate (no de-emphasis)
The S[x]TXLCTL0 and S[x]TXLCTL1 registers have default values that select the appropriate transmit
driver settings for each of the above modes. These default values may be modified to adjust the drive
levels. When the Physical layer of the port associated with the SerDes transitions dynamically across these
operating modes, the appropriate driver settings are applied to the SerDes automatically.
– For example, when the PHY operates in Full-swing mode at Gen 1 data rate with -3.5 dB de-
emphasis, the SerDes transmit settings are set to the values specified in the S[x]TXLCTL0 and
S[x]TXLCTL1 registers corresponding to that operating mode (e.g., Full-Swing mode at Gen 1
data rate with -3.5 dB de-emphasis). As the PHY changes data rate to Gen 2, the SerDes transmit
settings are automatically modified to the values specified in the S[x]TXLCTL0 and S[x]TXLCTL1
registers corresponding to the new operating mode (e.g., Full-Swing mode at Gen 2 data rate with
-3.5 dB de-emphasis).
Table 8.5 shows the register fields that control the SerDes transmit levels for the operation modes listed
above.
As shown in Table 8.5, there are three parameters that may be programmed to adjust the transmitter
drive levels (per-lane). These are:
– Fine De-emphasis Control (in the S[x]TXLCTL0 register)
– Coarse De-emphasis Control (in the S[x]TXLCTL1 register)
– Drive Level Control (in the S[x]TXLCTL1 register).
Modification of these settings takes an immediate effect on the SerDes. Therefore, the link does not
need to be retrained explicitly (i.e., via the link-retrain (LRET) bit in the port’s PCIELCTL register) in order
for these settings to take effect. Still, the user must be careful when modifying SerDes settings while the
port is in normal operating mode, as this may result in link instability.
PHY Operation Mode
Relevant
fields in
S[x]TXLCTL0
Relevant fields in
S[x]TXLCTL1
Voltage
Swing
Data
Rate
De-
emphasis
Fine De-
emphasis
Control
Drive Level /
Fine De-emphasis
Control
Full-Swing 2.5 GT/s -3.5 dB FDC_FS3DBG1 TDVL_FS3DBG1 /
CDC_FS3DBG1
Full-Swing 5.0 GT/s -3.5 dB FDC_FS3DBG2 TDVL_FS3DBG2 /
CDC_FS3DBG2
Full-Swing 5.0 GT/s -6.0 dB FDC_FS6DBG2 TDVL_FS6DBG2 /
CDC_FS6DBG2
Low-Swing 2.5 GT/s 0 dB N/A TDVL_LSG1
Low-Swing 5.0 GT/s 0 dB TDVL_LSG2
Table 8.5 SerDes Transmit Level Controls in the S[x]TXLCTL0 and S[x]TXLCTL1 Registers