
IDT Clocking
PES32NT24xG2 User Manual
2 - 6
January 30, 2013
Notes
• The global reference clock input (GCLK) must not use SSC.
• The GCLK’s frequency must be equal to or faster than the PxCLK’s frequency. This statement
does not include the n/-300 ppm deviations on either of these clocks. For example, the
GCLK’s frequency may be 100 Mhz - 300ppm while the PxCLK’s frequency is 100 Mhz +
300ppm. In addition, frequency increases, if any, introduced by the SSC component on PxCLK
must be correspondingly added to the GCLK frequency. Table 2.3 shows some allowed GCLK
and PxCLK combinations.
This results in the port clocking mode requirements summarized in Table 2.4.
Port Clocking Mode Selection
The port clocking mode used by a port is determined by the corresponding Port Clocking Mode (PxCLK-
MODE) field in the Port Clocking Mode (PCLKMODE) register. The initial port clocking mode of a port is
determined by the state of the CLKMODE[1:0] pins in the boot configuration vector as shown in Table 2.5.
This signal also determines the initial value of the Slot Clock Configuration (SCLK) field in each port’s PCI
Express Link Status (PCIELSTS) register.
The SCLK field controls the advertisement of whether or not the port uses the same reference clock
frequency as the link partner. The SCLK field may be modified by software (e.g., PCI Express configuration
requests, EEPROM, etc.) on a per-port basis, thus allowing for common or non-common clocked configura-
tions independently for each port. When the port operates in a multi-function mode (e.g., upstream switch
port with NT function, NT with DMA function, etc.), the SCLK field reports the same value for all functions of
the port.
Nominal
PxCLK
Frequency
PxCLK
SSC
Modulation
Effective
PxCLK
Frequency
Allowed
GCLK
Frequency
100 MHz + 300ppm
+0 / - 5000ppm
100 Mhz +300 / -
4700ppm
100 Mhz + / -
300ppm
100 MHz - 300ppm
+0 / - 5000ppm
100 Mhz -300 / -
5300ppm
100 Mhz + / -
300ppm
100 MHz + 300ppm
+0 / - 5000ppm
100 Mhz +300 / -
4700ppm
125 Mhz + / -
300ppm
100 MHz - 300ppm
+0 / - 5000ppm
100 Mhz -300 / -
5300ppm
125 Mhz + / -
300ppm
Table 2.3 GCLK and PxCLK frequencies when PxCLK has SSC
Port Clocking Mode
Clock Used by
Port for
Transmitting and
Receiving Data
Global Reference
Clock Input
Restrictions
Global Clocked
GCLK
none
Local Port Clocked
PxCLK
GCLK must not use SSC
Table 2.4 Port Clocking Mode Requirements
Summary of Contents for PCI Express 89HPES32NT24xG2
Page 20: ...IDT Table of Contents PES32NT24xG2 User Manual x January 30 2013 Notes...
Page 24: ...IDT List of Tables PES32NT24xG2 User Manual xiv January 30 2013 Notes...
Page 28: ...IDT List of Figures PES32NT24xG2 User Manual xviii January 30 2013 Notes...
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