IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 39 / 744

IDT PES32NT24xG2 Device Overview
PES32NT24xG2 User Manual 1 - 3 January 30, 2013
Notes
Figure 1.1 PES32NT24xG2 Block Diagram
The switch contains 24 ports labeled port 0 through port 23. All ports support 2.5 GTps (e.g., Gen 1) and
5.0 GTps (e.g., Gen 2) operation.
At a high level, the switch consists of four PCI Express (PCIe) stacks, two DMA modules, a switch core,
and peripheral blocks associated with SMBus functionality, GPIO functionality, reset, etc. A stack consists
of a logic that performs functions associated with the physical, data link, and transactions layers described
in the PCI Express Base Specification 2.1. In addition, a stack performs switch application layer functions
such as Transaction Layer Packet (TLP) routing using route map tables, processing configuration read and
write requests, non-transparent address translation, etc.
Two of the stacks are composed of eight x1 ports each. These stacks may be configured such that ports
are merged into one x8 port, two x4 ports, four x2 ports, eight x1 ports, or combinations in between. The
other two stacks are composed of four x2 ports each. These stacks may be configured such that ports are
merged into one x8 port, two x4 ports, four x2 ports, and combinations in between. Stack configurations are
described in section Stack Configuration on page 3-5. The DMA modules contain the logic and state asso-
ciated with DMA functionality. DMA functionality is introduced below and described in detail in Chapter 15,
DMA Controller.
The switch core is responsible for transferring TLPs between stacks. Its main functions are input buff-
ering, maintaining per port ingress and egress flow control information, port arbitration, scheduling, and
forwarding TLPs between ports. Since the switch represents a single architecture optimized for both fan-out
and system interconnect applications, its switch core is based on a non-blocking crossbar. Chapter 4
describes the switch core architecture and operation in detail.
Port Operating Modes
Ports operate independently from each other, even if the ports are in the same stack. Each port has
several operational modes that determine the behavior of the port, the PCI functions (e.g., PCI-to-PCI
bridge, Non-Transparent (NT) endpoint, and DMA endpoint) associated with the port, etc. Port operating
modes are introduced below and described in detail in Chapter 5, Switch Partition and Port Configuration.
Switch Core
GPIO
Controller
Master
SMBus
Interface
Slave
SMBus
Interface
Reset
Controller
GPIO
Master
SMBus
Slave
SMBus
Reset and Boot
Configuration
Vector
PCI Express Ports
DMA
Module
DMA
Module
Stack 2
SerDes
Stack 3
SerDes
PCI Express Ports
x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1
Stack 0
SerDes
x2 x2 x2 x2
Stack 1
SerDes
x2 x2 x2 x2