IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 715 / 744

IDT Usage Models
PES32NT24xG2 User Manual 26 - 5 January 30, 2013
Notes
ing steps take place.
2. Ports 0, 8, and 10 are migrated to partition 0.
Port 0 is configured as an upstream switch port in partition 0 by programming fields in the
SWPORT0CTL register appropriately. Ports 8 and 10 are configured as downstream switch ports in
partition 0 by programming fields in the SWPORT8CTL and SWPORT10CTL registers appropri-
ately.
For this configuration, there is no need to use the EEPROM Wait configuration block, as each port
is only configured once (i.e., the Wait configuration block is useful when applying multiple changes
to a port’s operating mode or to a partition’s state).
3. Similarly, ports 12, 16, and 18 are migrated to partition 1.
4. The state of partitions 0 and 1 is modified from disabled to active by programming the SWPARTxCTL
register appropriately.
This causes all ports in the partitions to operate normally (i.e., the ports exit the disabled state and
operate per the operating mode programmed in the SWPORTxCTL register).
If the PARTxPERSTN reset signal is not asserted, all port links are trained. Otherwise, links remain
down (i.e., in the Detect state) until the reset is de-asserted.
While the serial EEPROM loading executes, the switch is kept in quasi-reset mode (see section Partition
Resets on page 3-11). After EEPROM loading completes, enumeration software associated with partition 0
will find a switch with one upstream port (port 0) and two downstream ports (ports 8 and 10). No other ports
are logically visible in this partition.
Similarly, enumeration software associated with partition 1 will find a switch with one upstream port (port
12) and two downstream ports (ports 16 and 18). No other ports are logically visible in this partition.
Switch Partitioning via PCI Express Configuration Requests
Goal
Configure switch partitions via a port’s PCI Express interface using configuration requests.
Assumptions
– PES16NT8BG2 switch device.
– A switch manager root complex configures the switch using a customized BIOS.
• The switch manager is connected to port 0.
– Two partitions will be created:
• Partition 0 has ports 0, 8, and 10.
• Partition 1 has ports 12, 16, and 18.
– Ports 0 and 12 are upstream, x4 each.
– Ports 8, 10, 16, and 18 are downstream, x2 each.
– The stacks are configured at boot-time using the STKxCFG pins to achieve the above link widths.
– The switch boots in switch mode “Multi-partition with Unattached ports”.
– Serial EEPROM is not used.
Figure 26.4 shows the final configuration.