IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 69 / 744

IDT Reset and Initialization
PES32NT24xG2 User Manual 3 - 5 January 30, 2013
Notes
Refer to the PES32NT24xG2 Data Sheet for additional information on the signals that make up the boot
configuration vector.
Stack Configuration
As shown in Figure 1.1, the switch contains four stack blocks labeled Stack 0, Stack 1, Stack 2, and
Stack 3. Stacks 0 and 1 have four ports each, and stacks 2 and 3 have eight ports each. This provides a
total of 24 ports in the device, labeled port 0 through port 23. Table 3.3 lists the ports associated with each
stack.
Signal
May Be
Overridden
Name/Description
GCLKFSEL N Global Clock Frequency Select.
These pins specify the frequency of the GCLKP and GCLKN sig-
nals.
CLKMODE[1:0] Y Clock Mode.
These pins specify the clocking mode used by switch ports. See
Table 2.5 for a definition of the encoding of these signals. The
value of these signals may be overridden by modifying the Port
Clocking Mode (PCLKMODE) register.
RSTHALT Y Reset Halt.
When this pin is asserted during a switch fundamental reset
sequence, the switch remains in a quasi-reset state with the Mas-
ter and Slave SMBuses active. This allows software to read and
write registers internal to the device before normal device opera-
tion begins. The device exits the quasi-reset state when the RST-
HALT bit is cleared in the SWCTL register by an SMBus master.
Refer to section Switch Fundamental Reset on page 3-2 for further
details.
SSMBADDR[2:1]
1
1.
Note that the PES32NT24BG2 supports only SSMBADDR2.
N Slave SMBus Address.
SMBus address of the switch on the slave SMBus.
SWMODE[3:0] N Switch Mode.
These pins specify the switch operating mode. See section Switch
Modes on page 3-10.
STK0CFG[1:0] Y Stack 0 Configuration.
These pins select the configuration of stack 0 during a switch fun-
damental reset. Refer to section Stack Configuration on page 3-5
for further details.
STK1CFG[1:0] Y Stack 1 Configuration.
These pins select the configuration of stack 1 during a switch fun-
damental reset. Refer to section Stack Configuration on page 3-5
for further details.
STK2CFG[4:0] Y Stack 2 Configuration.
These pins select the configuration of stack 2 during a switch fun-
damental reset. Refer to section Stack Configuration on page 3-5
for further details.
STK3CFG[4:0] Y Stack 3 Configuration.
These pins select the configuration of stack 3 during a switch fun-
damental reset. Refer to section Stack Configuration on page 3-5
for further details.
Table 3.2 Boot Configuration Vector Signals