IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 174 / 744

IDT Transparent Switch Operation
PES32NT24xG2 User Manual 10 - 4 January 30, 2013
Notes
Interrupts
The switch’s PCI-to-PCI bridge functions may be configured to issue interrupts due to several condi-
tions. The interrupt sources each have a corresponding status bit in the PCI-to-PCI bridge function’s Inter-
rupt Status (P2PINTSTS) register.
– When an interrupt source requests service, the corresponding bit in the P2PINTSTS register is
set.
– An interrupt source may be masked from generating an interrupt by setting the corresponding
mask bit in the PCI-to-PCI Bridge Interrupt Mask (P2PINTMSK) register. By default, all interrupt
sources are masked.
– Once a bit corresponding to an interrupt source is set in the P2PINTSTS register, interrupts asso-
ciated with that source are inhibited until the bit is cleared in the P2PINTSTS register.
When a PCI-to-PCI bridge function detects the occurrence of an unmasked interrupt condition, an MSI
or legacy interrupt message is generated by the function per the rules in Table 10.2. The removal of the
interrupt condition occurs when unmasked status bit(s) causing the interrupt are masked or cleared.
The PES32NT24xG2 assumes that MSIs generated by the PCI-to-PCI bridge function target the root-
complex and always routes these transactions to the partition’s upstream link. Configuring the address
contained in the PCI-to-PCI bridge function’s MSIADDR and MSIADDRU registers to an address that does
not route to the partition’s upstream link and generating an MSI produces undefined results.
– An MSI generated by the PCI-to-PCI bridge function is never multicasted. Software must never
configure the address of an MSI generated by a PCI-to-PCI bridge function to fall within an
enabled multicast BAR aperture in the partition. Violating this requirement produces undefined
results.
Downstream Port Interrupts
The following are sources of downstream switch port interrupts and MSIs.
– Downstream switch port’s hot-plug controller.
– Link bandwidth notification capability (i.e., assertion of the LBWSTS or LABWSTS bits in the
PCIELSTS register when interrupt notification is enabled for these bits).
When a port is configured to generate INTx messages, only INTA is used. Note that the Interrupt Pin
register (INTRPIN) must be programmed accordingly.
Upstream Port Interrupts
The following are sources of upstream port interrupts and MSIs.
– Switch events
– Failover change initiated by the failover capability associated with the partition
– Failover change completed by the failover capability associated with the partition
– A temperature sensor alarm (see Chapter 19).
Unmasked
Interrupt
EN bit in
MSICAP
Register
INTXD bit
in PCICMD
Register
Action
Asserted 1 X MSI message generated
0 0 Assert_INTA message request generated
0 1 None
Negated 1 X None
0 0 Deassert_INTA message request generated
0 1 None
Table 10.2 PCI-to-PCI Bridge Function Interrupts