IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 306 / 744

IDT DMA Controller
PES32NT24xG2 User Manual 15 - 18 January 30, 2013
Notes
Aborting a DMA Operation
The processing of DMA descriptors by a DMA channel may be aborted by writing a one to the Abort
(ABORT) bit in the DMACxCTL register. When a DMA operation is aborted due to this condition, the
following actions take place:
– The DMA channel ceases to issue read requests. This includes DMA descriptor read requests and
data read requests.
– The DMA channel waits for completions, or completion time-outs, for all outstanding memory read
requests and processes these normally (e.g., completions for outstanding data read requests are
converted to memory write requests, completions for outstanding descriptor read requests are
processed). During this time, if the DMA finishes processing of a descriptor, the DMA may write-
back the descriptor prior to aborting the operation.
– The DMACxDPTRL/H registers point to the descriptor whose processing was aborted.
– All prefetched descriptors (see section Descriptor Prefetching on page 15-22) are discarded.
– When all of the above complete, the Abort (A) bit is set in the DMACxSTS register.
• If the DMA channel is idle when the Abort bit is written, then the A bit in the DMACxSTS register
is immediately set.
The processing of a DMA descriptors by a DMA channel may also be aborted as a side effect of error
detection during descriptor processing (refer to section Error Handling on page 15-27). When a DMA oper-
ation is aborted due to an error, the following actions take place:
– The DMA channel ceases to issue requests. This includes DMA descriptor read requests, source
address read requests, and memory write requests.
– The DMA channel waits for completions, or completion time-outs, for all outstanding memory read
requests. Received completions are discarded (i.e., the completions are not converted to memory
write requests).
– The DMACxDPTRL/H registers point to the descriptor whose processing was aborted.
– All prefetched descriptors are discarded.
– The bit corresponding to the error is set in the DMA Channel Error Status (DMACxERRSTS)
register.
– When all of the above complete, the Abort (A) bit and the Error (E) bit are set in the DMACxSTS
register.
Suspending and Resuming a DMA Operation
In some applications it is desirable to append descriptors to an active descriptor list (i.e., one that is
being processed by a DMA channel). The DMA channel suspend and resume capability provides a race-
free mechanism to perform this operation.
– For DMA descriptors located below 4 GB, it is possible to resolve the descriptor update/read race
condition without using the suspend/resume mechanism described in this section. Instead, the
more efficient mechanism described in section Dynamic Appending of Descriptor Lists on page
15-19 may be used.
– DMA channel suspend and resume requires that the DSCP field in the DMACxCFG register be
set to “process next descriptor” prior to enabling a DMA channel (see section Descriptor List
Processing on page 15-15), and descriptor chaining must not be enabled (see section Descriptor
Chaining on page 15-16).
The operation of a DMA channel may be suspended by writing a one to the Suspend (SUSPEND) bit in
the DMAxCTL register. When a DMA operation is suspended, the following actions take place:
– If the DMA is processing a descriptor, the DMA channel suspends processing after writing back
the updated descriptor status to memory, but without loading the DMACxDPTRL/H registers to
point to the next descriptor. Once the suspend operation takes place, the Suspend (S) bit is set in
the DMACxSTS register.