IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 207 / 744

IDT SMBus Interfaces
PES32NT24xG2 User Manual 12 - 3 January 30, 2013
Notes
Initialization from Serial EEPROM
During initialization from the optional serial EEPROM, the master SMBus interface reads configuration
blocks from the serial EEPROM and updates corresponding registers in the switch. Any software-visible
register in the device may be initialized with values stored in the serial EEPROM. All software-visible regis-
ters have a system address in the PES32NT24xG2’s global address space. Configuration blocks stored in
the serial EEPROM use this system address shifted right two bits (i.e., configuration blocks in the serial
EEPROM use DWord addresses and not byte addresses).
See Chapter 19 for the details on the system address and the global address space address map.
DWord addresses stored in the serial EEPROM are 16-bits wide (i.e., system address bits [17:2]).
Therefore, the serial EEPROM may be used to initialize the first 64 K DWords (256 KB) of the global
address space. All software-visible registers are located within this region and are therefore accessible via
the Serial EEPROM. Since configuration blocks are used to store only the value of those registers that are
initialized, a serial EEPROM much smaller than the total size of all of the configuration spaces may be used
to initialize the device. Any serial EEPROM compatible with those listed in Table 12.2 may be used to store
initialization values.
During serial EEPROM initialization, the master SMBus interface begins reading bytes starting at serial
EEPROM address zero. These bytes are interpreted as configuration blocks and sequential reading of the
serial EEPROM continues until the end of a configuration done block is reached or the serial EEPROM
address rolls over from 0xFFFF to 0x0. When a serial EEPROM address roll over is detected, loading of the
serial EEPROM is aborted, the Serial EEPROM Rollover (ROLLOVER) bit is set in the SMBus Status
(SMBUSSTS) register, and the RSTHALT bit is set in the SWCTL register.
A blank serial EEPROM contains 0xFF in all data bytes. When the switch is configured to initialize from
serial EEPROM and the first 256 bytes read from the EEPROM all contain the value 0xFF, then loading of
the serial EEPROM is aborted, the computed checksum is ignored, the Blank Serial EEPROM (BLANK) bit
is set in the SMBus Status (SMBUSSTS) register, and normal device operation begins (i.e., the device
operates in the same manner as though it were not configured to initialize from the serial EEPROM).
This is not considered an error. This behavior allows a board manufacturing flow that utilizes uninitial-
ized serial EEPROMs. See section Programming the Serial EEPROM on page 12-10 for information on in-
system initialization of the serial EEPROM.
All register initialization performed by the serial EEPROM is performed in DWord quantities. Byte values
may be modified by writing the entire DWord.
If during serial EEPROM initialization, an attempt is made to initialize a register that is not defined in a
configuration space (i.e., not defined in Chapter 19), then the Unmapped Register Access (URA) bit is set in
the SMBUSSTS register and the write is ignored. This is not considered an error.
Serial EEPROM Size
24C32 4 KB
24C64 8 KB
24C128 16 KB
24C256 32 KB
24C512 64 KB
Table 12.2 PES32NT24xG2 Compatible Serial EEPROMs