IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 68 / 744

IDT Reset and Initialization
PES32NT24xG2 User Manual 3 - 4 January 30, 2013
Notes
The operation of a switch fundamental reset using RSTHALT is illustrated in Figure 3.2.
Figure 3.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State
Boot Configuration Vector
A boot configuration vector consisting of the signals listed in Table 3.2 is sampled during a switch funda-
mental reset. Since the boot configuration vector is only sampled during a switch fundamental reset, the
state of the signals that make up the boot configuration vector is ignored outside of a switch fundamental
reset sequence.
While basic switch operation may be configured using signals in the boot configuration vector, advanced
switch features require more complex initialization. As noted in table Table 3.2, some of the initial values
specified by the boot configuration vector may be overridden by software, serial EEPROM, or an external
SMBus device.
– See section Slave SMBus Interface on page 12-22 for a description of the slave SMBus interface.
– See section Initialization from Serial EEPROM on page 12-3 for a description of the serial
EEPROM operation.
The state of all of the boot configuration signals in Table 3.2 sampled during a switch fundamental reset
may be determined from the Boot Configuration Status (BCVSTS) register.
SerDes
Slave SMBus
CDR Lock
Link Ready
Ready for Normal Operation
Ports held in Quasi-Reset Mode
Link Training PLL Reset & Lock
RSTHALT
Boot Vector sampled and RSTHALT bit in SWCTL register is set
RSTHALT bit in SWCTL cleared (e.g., via slave SMBus)
GCLK*
Vdd
PERSTN
1. Clock not shown to scale
> 100ns
Stable
Power
Stable
GCLK
~285
μ
s ~2
μ
s
< 100 ms
Ports begin to process TLPs normally