IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 194 / 744

IDT Transparent Switch Operation
PES32NT24xG2 User Manual 10 - 24 January 30, 2013
Notes
Completions (Routed by ID)
Completions for which there is no valid route across the switch (i.e., the completion can’t be forwarded)
are treated as unexpected completions. This includes the following cases:
– Completions that attempt to route back onto the link on which they were received, if ACS
Upstream Forwarding is disabled. When ACS Upstream Forwarding is enabled, such completion
TLPs are not treated as unexpected completions and are forwarded upstream.
– Completions received by a switch port that target a non-existent function in the upstream port.
– Completions received by a switch port that target a non-existent device in the upstream port’s bus
number.
– Completions received by a switch port that target a non-existent device or function in the switch’s
virtual PCI bus.
– Completions received by a switch port that fall within the bus aperture of the upstream port but are
not claimed by any downstream switch ports.
In addition, all completions that terminate within the PES32NT24xG2 (i.e., ones that target the upstream
switch port or any device/function on the virtual PCI bus within the switch) are treated as unexpected
completions by the port being targeted.
ID Routed Messages
– Messages that attempt to route back onto the link on which they were received, if ACS Upstream
Forwarding is disabled. When ACS Upstream Forwarding is enabled, such TLPs are not consid-
ered errors and are forwarded upstream.
– Messages that do not have a valid route through the switch.
– Messages that target a downstream switch port device number that does not exist or is not
enabled in the bond option.
– A Vendor Defined Type 0 message which targets an enabled switch port. Vendor Defined Type 1
messages that target a switch port are silently discarded by that port.
Error Emulation Control in the PCI-to-PCI Bridge Function
The PES32NT24xG2 provides the capability to emulate error occurrence in the AER uncorrectable and
correctable error status registers. Associated with the PCI-to-PCI bridge function are two error emulation
registers. The PCI-to-PCI Bridge Uncorrectable Error Emulation (P2PUEEM) and PCI-to-PCI Bridge
Correctable Error Emulation (P2PCEEM) registers allow emulation of errors in the PCI-to-PCI bridge func-
tion.
When a bit in these registers is set, it causes the hardware to emulate the detection of the corre-
sponding error. The detection of the error is handled as shown in Figure 6-2 of the PCI Express 2.1 base
specification (i.e., the corresponding error is logged in the AER status registers (i.e., AERUES or AERCES),
and reported to the root-complex).
– To allow emulation of advisory errors, the P2PUEEM register contains a bit named ADVISORYNF.
When this bit is set in conjunction with another bit in the P2PUEEM register, the hardware flags
the error as an advisory error and handles it according to Figure 6-2 of the PCI Express 2.1 base
specification. Refer to the description of this bit for details.
Since the error emulation does not involve an actual TLP, the AER Header Log registers
(AERHL[1:4]DW) in the switch have RWL type, such that they may be modified by software to emulate the
capturing of the TLP’s header.
Error Emulation Usage and Limitations
The following are some usage guidelines and limitations associated with error emulation.
– To emulate the detection of a correctable error:
• The desired error bit must be set in the P2PCEEM register.
– To emulate the detection of an uncorrectable fatal error:
• The desired error bit must be set in the P2PUEEM register.